Wheel speed measuring circuit

• US 4,420,814 A
• Filed: 06/22/1981
• Issued: 12/13/1983
• Est. Priority Date: 06/27/1980
• Status: Expired due to Term

• Current Assignee: Bosch Braking Systems Corporation (Robert Bosch GmbH)
• Original Assignee: Nippon Air Brake Co., Ltd. (Nabtesco Corporation)
• Inventors: Inoue, Teruo, Arikawa, Tetsuro, Takiue, Yukihiro
• Primary Examiner(s): Chin, Gary
• Application Number:
  US06/275,974
• Time in Patent Office: 904 Days
• Field of Search: 364/426, 364/565, 235/92 FQ, 235/92 TF, 235/92 TC, 324/160, 324/161, 324/163, 324/166, 361/236, 361/240, 361/242, 303/20, 303/91, 303/94, 303/95, 303/105
• US Class Current: 702/148
• CPC Class Codes: G01P 3/489 Digital circuits therefor

Abstract

A wheel speed measuring circuit includes a counter controlled by a wheel speed signal having a frequency proportional to the rotational speed of the wheel sensed by a wheel speed sensor associated with a wheel; a comparator for comparing the digital output of the counter with a predetermined digital value; a wheel speed generating circuit for generating a digital output corresponding to the rotational speed of the wheel on the basis of the output of the comparator; and a pulse generator for generating pulses of a frequency proportional to the digital output of the wheel speed generating circuit, the pulse generator receiving the digital output of the wheel speed generating circuit, wherein the counter receives the output pulses of the pulse generator to count the output pulses thereof for the period of the wheel speed signal or for a time interval relating to the period of the wheel speed signal, and the digital output of the counter is compared with the predetermined digital value in the comparator.

Claims

1. A wheel speed measuring circuit comprising:

(A) a counter controlled by a wheel speed signal having a frequency proportional to the rotational speed of the wheel, sensed by a wheel speed sensor associated with a wheel;

(B) a comparator for comparing the digital output of said counter with a predetermined digital value M, said comparator generates a first output signal when the output of said counter is less than the value M and a second output signal when the output of said counter is greater than the value M;

(C) a wheel speed generating circuit operatively connected to said comparator for generating a digital output corresponding to the rotational speed of the wheel, wherein said digital output of the wheel speed generating circuit is increased from a pre-existing digital output of said wheel speed generating circuit in response to said first comparator output signal and decreased from said pre-existing digital output in response to said second comparator output signal; and

(D) a pulse generator for generating pulses of a frequency proportional to said digital output of the wheel speed generating circuit, said pulse generator receiving said digital output of the wheel speed generating circuit, wherein said counter receives the output pulses of said pulse generator to count said output pulses for each period of the wheel speed signal or for a time interval relating to each period of the wheel speed signal, and the digital output of said counter is compared when said predetermined digital value in said comparator.

2. A wheel speed measuring circuit according to claim 1, in which said wheel speed generating circuit includes an UP/DOWN counter, and said UP/DOWN counter receives timing pulses of a predetermined frequency from a timing pulse generator as a count-up signal or a count-down signal in accordance with said first and second output signals generated by said comparator.

3. A wheel speed measuring circuit according to claim 2, in which a compensation circuit is connected between said counter and said comparator, said compensation circuit receives said count-up signal or said count-down signal to equalize the digital output supplied to the comparison input terminals of said comparator with said predetermined digital value M thereof.

4. A wheel speed measuring circuit according to claim 3, in which, when the comparison output of said comparator represents that the comparison input value at said input terminals is smaller than said perdetermined digital value M, said UP/DOWN counter receives said timing pulses as said count-up signal, and when the comparison output of said comparator represents that the comparison input value is larger than said perdetermined digital value M, said UP/DOWN counter receives said timing pulses as said count-down signal.

5. A wheel speed measuring circuit according to claim 4, in which said UP/DOWN counter is preset to a predetermined digital value No corresponding to the minimum wheel speed to be measured, and a gate circuit is connected between said UP/DOWN counter and said timing pulse generator, said timing pulses as the countdown signal being cut off from said UP/DOWN counter by said gate circuit while the wheel speed is lower than said minimum wheel speed.

6. A wheel speed measuring circuit according to claim 5, in which said gate circuit includes a NOR gate, and all of the output terminals of said UP/DOWN counter except the output terminals thereof which become high at said digital value NO are connected to input terminals of said NOR gate.

7. A wheel speed measuring circuit according to claim 4, in which said compensation circuit comprises an UP/DOWN counter which latches the digital output of said counter every said period of the wheel speed signal or every said time interval relating to the period of the wheel speed signal as sensed by said wheel speed sensor.

8. A wheel speed measuring circuit according to claim 2, in which said pulse generator comprises a binary rate multiplier receiving clock pulses of a predetermined frequency.

9. A wheel speed measuring circuit according to claim 1, in which said wheel speed signal is formed from rectangular wave obtained by wave-shaping of output of a wheel speed sensor associated with the wheel.

10. A wheel speed measuring circuit according to claim 2, in which said wheel speed measuring circuit further includes an gate circuit, and a failure detecting circuit comprising a second counter and a second comparator;

said UP/DOWN counter is preset to a first predetermined digital value No'"'"' larger than a second predetermined digital value No corresponding to the minimum wheel speed to be measured, at the time t₁ when power is supplied to said wheel speed measuring circuit;

said timing pulses as the countdown signal are supplied to said UP/DOWN counter, then cut off from said UP/DOWN counter at the time t₂ when said UP/DOWN counter counts down to No, by said gate circuit;

said second counter counts said timing pulses for a time interval between the time t₁ when the power is supplied to said wheel speed measuring circuit, and the time t₂ when said UP/DOWN counter counts down to No;

the count result of said second counter is compared with a predetermined digital value, or a predetermined range in said second comparator; and

when said count result of the second counter is not equal to said predetermined digital value or beyond said predetermined range, said failure detecting circuit generates a failure signal.

11. A wheel speed measuring circuit according to claim 10, in which said gate circuit includes a NOR gate, and all of the output terminals of said UP/DOWN counter except the output terminals thereof at which output signals become high at said digital value No, are connected to input terminals of said NOR gate.

12. A wheel speed measuring circuit according to claim 11, in which said time interval between the times t₁ and t₂ are detected by a flip flop.

13. A wheel speed measuring circuit according to claim 12, in which said flip flop is set at the time t₁ when power is supplied to said wheel speed measuring circuit, and reset with the output of said NOR gate.

14. A wheel speed measuring circuit according to claim 13, in which an output terminal of said flip flop is connected to one input terminal of an AND gate, said timing pulse generator is connected to another input terminal of said AND gate, and the output of said AND gate is supplied to said second counter.

15. A wheel speed measuring circuit according to claim 14, in which the output terminal of said flip flop is connected to the most significant bit (MSB) terminal of the comparison input terminals of said first-mentioned comparator.