Multi-frequency busy signal synthesizing circuitry
First Claim
1. Circuitry for synthesizing a tone output signal that approximates a multi-frequency signal comprised of a first tone having a first predetermined frequency and a second tone having a second predetermined frequency, said synthesizing circuitry comprising:
- a signal source for generating a clock signal having a predetermined frequency that is greater than said first predetermined frequency and said second predetermined frequency;
means for generating a control signal alternately having first and second states at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between said first predetermined frequency and said second predetermined frequency; and
means coupled to the clock signal source and generating means for dividing the clock signal by a first number in response to the first state of the control signal to produce the tone output signal having a first frequency greater than said first predetermined frequency and by a second number in response to the second state of the control signal to produce the tone output signal having a second frequency that is greater than said second predetermined frequency.
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Accused Products
Abstract
Circuitry for synthesizing a busy or reorder tone comprised of a first tone having a frequency of 770 Hz and a second tone having a frequency of 1150 Hz is described. The inventive synthesizing circuitry requires only one clock oscillator, whose output is coupled to a programmable divider. The programmable divider is switched between two divisor numbers at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between 770 Hz and 1150 Hz. In the preferred embodiment, the programmable divider output is switched between frequencies of 1250 Hz and 883.3 Hz at a 500 Hz rate. The programmable divider output is then interrupted at a 2 Hz rate to provide the synthesized busy signal. The inventive synthesizing circuitry may be advantageously utilized in mobile or portable radios for providing a busy signal that sounds essentially identical to a fast busy or reorder tone comprised of two tones.
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Citations
8 Claims
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1. Circuitry for synthesizing a tone output signal that approximates a multi-frequency signal comprised of a first tone having a first predetermined frequency and a second tone having a second predetermined frequency, said synthesizing circuitry comprising:
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a signal source for generating a clock signal having a predetermined frequency that is greater than said first predetermined frequency and said second predetermined frequency; means for generating a control signal alternately having first and second states at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between said first predetermined frequency and said second predetermined frequency; and means coupled to the clock signal source and generating means for dividing the clock signal by a first number in response to the first state of the control signal to produce the tone output signal having a first frequency greater than said first predetermined frequency and by a second number in response to the second state of the control signal to produce the tone output signal having a second frequency that is greater than said second predetermined frequency. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for synthesizing a tone output signal that approximates a multi-frequency signal comprised of a first tone having a first predetermined frequency and a second tone having a second predetermined frequency, said method comprising the steps of:
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(a) generating a clock signal having a frequency that is greater than said first predetermined frequency and said second predetermined frequency; (b) generating a control signal alternately having first and second states at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between said first predetermined frequency and said second predetermined frequency; and (c) dividing the clock signal by a first number in response to the first state of the control signal to produce the tone output signal having a first frequency greater than said first predetermined frequency and by a second number in response to the second state of the control signal to produce the tone output signal having a second frequency that is greater than said second predetermined frequency. - View Dependent Claims (8)
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Specification