Semiconductor device having a reduced surface field strength

• US 4,422,089 A
• Filed: 12/22/1980
• Issued: 12/20/1983
• Est. Priority Date: 09/08/1980
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Ludikhuize, Adrianus W., Appels, Johannes A., Vaes, Henricus M. J.
• Primary Examiner(s): Davie, James W.
• Application Number:
  US06/219,160
• Time in Patent Office: 1,093 Days
• Field of Search: 357/22, 357/89, 357/90, 357/22 R, 357/23 R, 357/23 HV, 357/13, 357/35
• US Class Current: 257/492
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/7322 having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A semiconductor device of the "RESURF" type has a substrate region and a superimposed semiconductor layer which forms a p-n junction with the substrate region. The semiconductor layer has an island-shaped region which is depleted at least locally up to the surface at a reverse voltage applied across the p-n junction which is well below the breakdown voltage of the p-n junction. According to the invention the island-shaped part of the semiconductor layer over at least a part of its area has a doping profile in the vertical direction with at least two overlying layer portions with different average net doping concentrations and of the same or opposite conductivity type, so as to increase the current-carrying capacity of the semiconductor layer.

Claims

1. A semiconductor device having a semiconductor body comprising a substrate region of a first conductivity type, a surface-adjoining layer-shaped semiconductor region provided at the surface of said substrate region, at least a substrate region-adjoining part of said layer-shaped semiconductor region being of a second conductivity type opposite to that of said first type and forming a p-n junction with said substrate region, an island-shaped part of said layer-shaped semiconductor region being bounded laterally by a separation region which extends from the surface over substantially the whole thickness of the semiconductor region, at least a first zone of a semiconductor circuit element being provided within said island-shaped part, the overall net doping of the second conductivity type of said layer-shaped semiconductor region in atoms per unit of surface area being sufficiently small such that when a voltage in the reverse direction is applied across said p-n junction the depletion zone within the island-shaped part will extend at least locally from said p-n junction up to the surface at a voltage which is lower than the breakdown voltage of the p-n junction, at least a part of said island-shaped part of the layer-shaped semiconductor region having a doping profile comprising at least two overlying layer portions of different average net doping concentrations between said substrate and said surface.

2. A semiconductor device as claimed in claim 1, characterized in that at least the substrate region-adjoining part of the layer-shaped semiconductor region is more highly doped than the substrate region.

3. A semiconductor device as claimed in claim 1 or 2, characterized in that said layer portions with different net doping concentrations extend up to the edge of the island-shaped region.

4. A semiconductor device as claimed in claim 1 or 2, characterized in that the layer-shaped semiconductor region is entirely of the second conductivity type.

5. A semiconductor device as claimed in claim 4, characterized in that the layer portion having the highest average doping concentration adjoins the substrate region.

6. A semiconductor device as claimed in claim 5, characterized in that the layer portion having the highest average doping concentration is formed by a layer of the second conductivity type implanted in the substrate.

7. A semiconductor device as claimed in claim 4, characterized in that the layer portion having the highest average doping concentration adjoins the surface.

8. A semiconductor device as claimed in claims 1 or 2, characterized in that the layer-shaped semiconductor region comprises at least a first layer portion of the second conductivity type adjoining the substrate region and at least a second layer portion of the first conductivity type provided thereon, the last, surface-adjoining layer portion having a sufficiently low doping level to be fully depleted at a voltage across said p-n junction which is lower than the breakdown voltage, the layer portion of the first conductivity type being connected to a potential which is substantially equal to the potential of the substrate region.

9. A semiconductor device as claimed in claim 8, characterized in that the layer portion of the first conductivity type are connected to the substrate region by means of semiconductor zones of the first conductivity type.

10. A semiconductor device as claimed in claim 8, characterized in that the layer-shaped semiconductor region consists of a number of successive layers of alternate conductivity types, in which the layer portions of the second conductivity type are mutually connected to substantially the same potential.

11. A semiconductor device as claimed in claim 8, characterized in that the second layer portions adjoin the surface.

12. A semiconductor device as claimed in claim 11, characterized in that the second layer portion is noncontinuous.

13. A semiconductor device as claimed in claim 1 or 2, characterized in that at least one of the said layer portions is formed by an epitaxially grown layer.

14. A semiconductor device as claimed in claim 1 or 2, characterized in that the separation region is formed by a semiconductor zone of the first conductivity type.

15. A semiconductor device as claimed in claims 1 or 2, characterized in that the separation region is formed by a pattern of electrically insulating material at least partly countersunk in the semiconductor body.

16. A semiconductor device as claimed in claim 1 or 2, characterized in that the substrate region has a doping concentration of at least 10¹⁴ atoms per cm³ and at most 10¹⁵ atoms per cm³ and that the overall net doping of the layer-shaped semiconductor region is at least 8×

10¹¹ atoms per cm² and at most 1.5×

10¹² atoms per cm².

17. A semiconductor device as claimed in claim 1 or 2, characterized in that the layer-shaped region forms the channel region of a junction field effect transistor (JFET), said JFET having surface-adjoining, spaced-apart source, gate, and drain regions.

18. A semiconductor device as claimed in claim 1 or 2, further comprising a lateral self-aligned insulated gate field effect transistor and characterized in that the layer-shaped region adjoins the drain zone and the channel region of said lateral self-aligned insulated gate field effect transistor.

19. A semiconductor device as claimed in claim 1 or 2, characterized in that a part of the layer-shaped region froms the collector zone of a bipolar transistor, said transistor having surface-adjoining, adjacent base and emitter zones.

20. A semiconductor device as claimed in claims 1 or 2, characterized in that the layer-shaped semiconductor region comprises at least a first layer portion of the second conductivity type adjoining the substrate region and at least a second layer portion of the first conductivity type provided thereon, the layer portions of the first conductivity type being connected to a potential which is substantially equal to the potential of the substrate region, and means for causing the top surface-adjoining layer portion to be fully depleted at a voltage across said p-n junction which is lower than the breakdown voltage.

21. A semiconductor device as claimed in claim 20, characterized in that said means comprises a sufficiently low doping concentration of said layer portion.