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Device for the digital transmission and display of graphics and/or of characters on a screen

  • US 4,424,572 A
  • Filed: 09/09/1980
  • Issued: 01/03/1984
  • Est. Priority Date: 09/12/1979
  • Status: Expired due to Term
First Claim
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1. In a device for a digital transmission and display of graphics on a screen, comprising at least two telewriting terminals connected by a transmission network, each terminal being associated with a graphic acquisition device and with a unit for display on a screen, each terminal being organized around a digital data processing circuit connected to said graphic acquisition device via a first interface and to the network via a second interface, the circuit receiving from one or the other interface digital data comprising in particular coordinates X and Y of points composing graphics and display codes or information enabling a display of said graphics, each terminal further comprising a unit for storing these digital data, inserted between the data processing circuit and a display control module, said module controlling the display of said points by said unit for display. each terminal comprises:

  • (a) a plurality of storage assemblies, each storage assembly being constituted by a random access memory (RAM) of sufficient capacity to be able to contain informations corresponding to a complete image covering said screen, said memory having a writing input, a read-out output, a validation input and an addressing input, each storage assembly comprising a logic function generator having a control input, a first signal input, a second signal input connected to the read-out output of the random access memory and a signal output connected to the writing input of said memory signal output conveying a word to be written which is a logic function of a word applied to the first signal input and a word applied to the second input;

    (b) an address computing circuit receiving, via the data processing circuit, for each current point written on the graphic acquisition device, said coordinates X and Y of said point and delivering on octet Pi comprising only one binary element equal to "1", said octet being applied to the first input of the logic function generator, and a digital signal constituting an address for said octet Pi ;

    (c) a circuit for controlling writing and read-out in the storage assemblies, comprising;

    (c1) a selector circuit having an input connected to the output of the data processing circuit from which it receives four signals;

    a first signal which is said octet Pi, a second signal which is a validation code formed by as many binary elements as there are storage assemblies, a third signal which is a logic function code, and a fourth signal which is an address of said octet Pi, the selector having first, second, third and fourth outputs and being adapted to direct the four signals that it receives respectively on said four outputs,(c2) a first store having an input connected to the first output of said selector circuit from which it receives the octet Pi and an output connected to the signal input of the logic function generator,(c3) a second store having an input connected to the second output of said selector circuit, from which it receives binary elements forming a validation code, said second store containing as many storage binary cells as there are storage assemblies, said cells each being connected to an output connection, said output being connected to said validation input of one of said random access memories, said memories therefore all being able to be validated in parallel;

    (c4) a third store having an input connected to the fourth output of said selector circuit, from which it receives the address of the octet Pi and having an output connected to the addressing inputs of the storage assemblies,said storage assemblies, computing circuit and controlling circuit allowing simultaneous access to said plurality of storage assemblies validated in parallel to write therein binary information at a desired address taking into account the information already written at this address according to predetermined functions.

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