Mask programmable read-only memory stacked above a semiconductor substrate
First Claim
1. A mask programmable read-only memory having memory cells stacked above a semiconductor substrate comprised of:
- a. address decode means integrated into a surface of said substrate for addressing said cells in said memory;
b. a first insulating layer covering said address decode means and said surface;
c. an array of spaced-apart memory cell select lines on said first insulating layer including;
i. a plurality of spaced-apart semiconductor lines formed on said first insulating layer;
ii. a second insulating layer formed over said semiconductor lines; and
iii. a plurality of spaced-apart metal lines formed over said second insulating layer and arranged orthogonal to said semiconductor lines;
d. outputs from said address decode means respectively coupled through said first insulating layer to said select lines wherein each cell of said memory is formed at an intersection of one of said semiconductor lines and one of said metal lines and further includes a mask selectable Schottky diode at select ones of said intersections representative of the information in said cell.
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Accused Products
Abstract
In the disclosed read-only memory, address decode means for addressing information in the memory lie in a semiconductor substrate; an insulating layer covers the address decode means; an array of spaced-apart metal lines and semiconductor lines lies on the insulating layer over the address decode means; outputs from the address decode means respectively couple through the insulating layer to the metal lines and to the semiconductor lines; and a plurality of mask selectable electrical contacts between the metal lines and semiconductor lines forms a matrix of mask selectable diodes over the insulating layer representative of the information in the memory.
94 Citations
18 Claims
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1. A mask programmable read-only memory having memory cells stacked above a semiconductor substrate comprised of:
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a. address decode means integrated into a surface of said substrate for addressing said cells in said memory; b. a first insulating layer covering said address decode means and said surface; c. an array of spaced-apart memory cell select lines on said first insulating layer including; i. a plurality of spaced-apart semiconductor lines formed on said first insulating layer; ii. a second insulating layer formed over said semiconductor lines; and iii. a plurality of spaced-apart metal lines formed over said second insulating layer and arranged orthogonal to said semiconductor lines; d. outputs from said address decode means respectively coupled through said first insulating layer to said select lines wherein each cell of said memory is formed at an intersection of one of said semiconductor lines and one of said metal lines and further includes a mask selectable Schottky diode at select ones of said intersections representative of the information in said cell. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A diode memory fabricated over an integrated circuit in a semiconductor substrate comprising:
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a. a first insulating layer formed over said integrated circuit; b. first spaced-apart conductors formed on said first insulating layer and being made of a double layer polycrystalline material wherein a first layer adjacent said first insulating layer is comprised of N+ polycrystalline material having a relatively high concentration of dopant material and an adjacent overlying second layer is comprised of N- polycrystalline material having a relatively low concentration of dopant material; c. a second insulating layer formed on said first insulating layer covering said first conductors except at predetermined locations; d. second spaced-apart conductors formed on said second insulating layer so as to cross over and above said first spaced-apart conductors; e. a plurality of Schottky diodes formed between said first and second conductors at said predetermined locations; and f. electrical connection means passing through said insulating layers for electrically interconnecting particular ones of said first and second conductors to particular portions of said integrated circuitry. - View Dependent Claims (8, 9, 10, 11)
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12. An electrical structure incorporating a Schottky diode comprising:
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a. an insulating layer; b. an N+ polycrystalline layer having a relatively high concentration of dopant material formed on said insulating layer; c. an N- polycrystalline layer having a relatively low concentration of dopant material formed on said N+ polycrystalline layer; d. a metal layer provided on said N- polycrystalline layer forming a compound therewith such that a Schottky barrier junction is created at the interface between said compound and said N- polycrystalline layer; e. a barrier metal layer formed on said compound; and f. a conductive metal layer formed on said barrier metal layer. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification