Implantable externally programmable microprocessor-controlled tissue stimulator

• US 4,424,812 A
• Filed: 10/09/1980
• Issued: 01/10/1984
• Est. Priority Date: 10/09/1980
• Status: Expired due to Term

• Current Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Cordis Corporation (Cardinal Health, Inc.)
• Inventors: Lesnick, Alan F.
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US06/195,665
• Time in Patent Office: 1,188 Days
• Field of Search: 128/419 PG, 128/421, 128/422
• US Class Current: 607/30
• CPC Class Codes: A61N 1/37211 Means for communicating with stimulators
• CPC Class Codes: A61N 1/37252 Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data

Abstract

A microprocessor-controlled implantable programmable stimulator includes a pulse generator external to the microprocessor for producing stimulation output pulses to multiple electrodes. A microprocessor implements a stored program data processing system which sets latches to establish pulse parameters. Externally transmitted parameter data is decoded by the processing system, confirmed by two-way telemetry and loaded into control registers. The microprocessor obtains corresponding stored values from parameter tables in a ROM, and then sets amplitude, rate and width latches. The pulse rate and width latches preset separate counters operated by respective slow and fast clocks. To conserve power, the fast clock is enabled only briefly each time the rate counter times out. When running, the fast clock replaces the slow clock input to the microprocessor. The timed-out signal from the rate counter generates an interrupt request which calls a subroutine to reprogram electrode polarity before enabling each output pulse. This system allows several electrodes to be alternately connected as anodes and cathodes. An internal machine cycle counting routine disables the interrupt capability during the off portion of a scheduled on/off cycle and programs the rate to a fixed minimum.

Claims

1. An implantable tissue stimulator, comprising

at least one stimulation electrode

a digital data processor including stored program means containing program instructions and processing means with command outputs and an interrupt request input for fetching and executing instructions from said stored program means, said stored program means containing means defining instructions for causing said processing means to generate a pulse command output in response to an interrupt request,

pulse timing means for producing an interrupt request at predetermined intervals, and

pulse generator means responsive to said pulse command output for applying a corresponding stimulation pulse to said electrode.

2. The stimulator of claim 1, wherein said stored program means contains instructions for causing said processing means to execute a routine for timing a preprogrammed on/off cycle and for disabling the interrupt capability of said processing means during the off portion of the cycle.

3. The stimulator of claim 2, wherein said pulse timing means has means responsive to a rate output command from said processing means for establishing the interval between successive output signals, and said stored program means contains instructions for causing said processing means to issue a rate output command to lower the rate of said pulse timing means during the off portion of the cycle.

4. The stimulator of claim 1, wherein said pulse timing means and pulse generator means are external to said digital data processor.

5. The stimulator of claim 1, further comprising a slow clock and a fast clock, and wherein said pulse timing means and said pulse generator means include first and second presettable down counting means respectively each producing a timed-out output indicative of counting down to zero from a preset number, and each having a preset input and a clock input, said first and second counting means clock inputs being connected to said slow clock and said fast clock respectively, the timed-out output of said first counting means forming said output signal to said interrupt request input, means for enabling said fast clock and for recycling said first counting means in response to said timed-out output of said first counting means, said pulse generator means including logic means for beginning a stimulation output pulse in response to said pulse command output by enabling said second down counting means and ending said pulse in response to the timed-out output of said second counting means.

6. The stimulator of claim 5, wherein said stored program means contains instructions for causing said processing means to execute a routine for timing an on/off cycle and for disabling the interrupt capability of said processing means during the off portion of the cycle.

7. The stimulator of claim 5, wherein said processing means further includes means for storing a variable programmed rate and said stored program means contains instructions for causing said processing means to apply a corresponding rate input to said preset input of said first counting means.

8. The stimulator of claim 7, wherein said stored program means contains instructions for causing said processing means to execute a routine for timing an on/off cycle and for disabling the interrupt capability of said processing means and applying a fixed minimum rate input to said preset input of said first counting means during the off portion of said cycle and then reprogramming said preset input of said first counting means to the variable programmed rate and re-enabling the interrupt capability during each on portion of the cycle.

9. The stimulator of claim 5, wherein said processing means has a clock input, and further comprising logic means for connecting said processing means clock input to said fast clock when said fast clock is enabled and to said slow clock when said fast clock is not enabled.

10. The stimulator of claim 8, wherein the frequency of said clock input determines the length of the period of a machine cycle for said processing means, said routine for timing an on/off cycle includes instructions for generating and storing an on number as a function of both a programmed on time and said variable programmed rate, and means for incrementing said number once for every n machine cycles where n is an integer, until the incremented number reaches a predetermined level, whereby the on portion of the cycle is timed, the on number being determined so as to compensate for the rate variable frequency of fast clock machine cycles.

11. The stimulator of claim 10, wherein said on/off cycle timing means further includes means for storing an off number which is a function of desired off time and said fixed minimum rate, and means for incrementing the off number once for every n machine cycles, where n is an integer, until the incremented number reaches a predetermined level, whereby the off portion of the cycle, during which the fast clock is enabled at regular intervals, is timed.

12. The stimulator of claim 1, further comprising a plurality of variable output pulse parameter latch means for determining the parameters of said output pulses from said pulse generator means each having means responsive to a corresponding command output of said processing means for establishing a given set of specific pulse parameters, said stored program means containing instructions for causing said processing means to issue command outputs corresponding to said pulse parameters.

13. The stimulator of claim 12, wherein said processor further includes a plurality of pulse parameter registers and said processing means has an external input for receiving externally generated pulse parameter data, said stored program means containing instructions for causing said processing means to decode said external data and store corresponding data in said pulse parameter registers, and transfer means for applying the data in said pulse parameter registers to said pulse parameter latches.

14. The stimulator of claim 13, wherein said processor includes a data bus, said latch means being connected to said data bus, said stored program means containing instructions for causing said processing means to issue a parameter-type identification command output and for simultaneously placing a parameter value output on said data bus, said latch means obtaining the corresponding parameter value output in response to the respective parameter-type identification command output.

15. The stimulator of claim 13, wherein said stored program means further contains a plurality of fixed pulse parameter tables and instructions for causing said processing means to obtain the stored values from said parameter tables corresponding to the external transmitted data, said transfer means applying the value obtained from the parameter table to said pulse parameter latch means.

16. The stimulator of claim 15, wherein said stored program means contains instructions for causing said processing means to execute a routine for timing an external preprogrammed on/off cycle and for disabling the interrupt capability of said processing means during the off portion of the cycle, said processor further including an on register and an off register, said stored program means parameter table including a plurality of off numbers and a plurality of on numbers and said stored program means further containing instructions for causing said processing means to obtain a corresponding on number and off number from said stored table in accordance with external data and for placing the on number and off number in said on register and said off register, respectively.

17. The stimulator of claim 16, wherein said processor further includes a cycle register, said stored program means further containing instructions for causing said processing unit to place the on number in said cycle register at the end of the off cycle and for incrementing said cycle counter at regular intervals until the count in said cycle counter is indicative of the end of said on cycle and then for disabling the interrupt capability of said processing means and placing said off number in said cycle counter and decrementing said off number at regular intervals until the number in said cycle counter indicates the end of the off cycle and then enabling the interrupt capability of said processing means and repeating the cycle.

18. The stimulator of claim 1, further comprising

an electrode connection controller interposed between the output of said pulse generator means and said electrode, and

electrode connection latch means for establishing whether said electrode is connected as an anode or connected as a cathode, said latch means being responsive to a corresponding command output of said processing means.

19. The stimulator of claim 18, wherein said stored program means interrupt service subroutine includes instructions for signalling said electrode connection latch means to reprogram the electrode connections prior to each output pulse.

20. The stimulator of claim 19, wherein said latch means is responsive to said pulse command output.

21. The stimulator of claim 19, wherein said processor further includes an electrode 1 register and an electrode 2 register indicative of the connection status for said electrode on respective alternate output pulses, said interrupt service subroutine in said stored program means containing instructions for signalling said electrode connection latch means in accordance with the contents of said electrode 1 register and electrode 2 register on alternate stimulation output pulses, respectively.

22. The stimulator of claim 21, wherein there are a plurality of electrodes whose connection status on alternate output pulses is indicated by the contents of said electrode 1 register and electrode 2 register, respectively, there being a plurality of said electrode connection controllers and electrode connection latch means corresponding respectively to said electrodes and operable in accordance with the contents of said electrode registers.

23. The stimulator of claim 22, further comprising a metallic case connected to one of said electrode connection controllers for serving as an additional electrode.

24. The stimulator of claim 23, wherein said processor further includes a case 1 register and a case 2 register, the contents of said case registers being indicative of the connection status of said case on alternate stimulation output pulses, respectively, said stored program means interrupt service subroutine including further instructions for causing said processing means to signal said case latch means in accordance with the contents of said case 1 register or said case 2 register immediately prior to alternate corresponding stimulation output pulses, respectively.