Variable delay circuit for emulating word line delay

• US 4,425,633 A
• Filed: 10/06/1980
• Issued: 01/10/1984
• Est. Priority Date: 10/06/1980
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: Mostek Corporation (Rtx Corporation)
• Inventors: Swain, William J.
• Primary Examiner(s): Stellar, George G.
• Application Number:
  US06/194,334
• Time in Patent Office: 1,191 Days
• Field of Search: 365/194, 365/195, 365/198, 333/138, 333/139, 333/140, 333/164, 328/56, 328/167
• US Class Current: 365/194
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor memory having an address buffer (10), row decoder (12), word lines (16), bit line (20) and sense amplifier (22) for accessing individual memory cells in an array of memory cells. In order to emulate worst case delays experienced in the word lines in accessing the last cells in the rows in order to prevent the sense amplifiers (22) from reading the bit lines (20) too soon, a tunable delay circuit (30) delays actuation of the sense amplifier. This circuit is divided into a plurality of impedance section with associated parasitic capacitance where groups of sections are bypassed by switching devices such as MOS transistors. The delay of a signal propagating through this tunable delay circuit can be varied by bypassing varying numbers of the sections with the switching devices.

Claims

1. A variable delay circuit for optimizing emulation of word line delays in semiconductor memories having a distributed resistive delay line comprised of:

a plurality of nodes interspersed along the length of said distributed resistive delay line and defining a plurality of individual sections of the delay line, and wherein the resistance from each node to a common node at the end of the delay line is a fraction of the total resistance of the entire line;

a plurality of switching devices with each switching device connected between one of said nodes and common node for bypassing a preselected section or group of sections of the distributed resistive delay time.

2. A variable delay circuit as claimed in claim 1 wherein the switching devices are MOS transistors having source and drain terminals connecting one of the nodes to common node and having gate terminals for controlling whether a high or low impedance appears between the source and drain terminals.

3. A variable delay circuit as claimed in claim 2 wherein the gate of each MOS transistor is connected to a resistive voltage divider having two ends and a middle node, said voltage divider having one end connected to a first voltage source and the other end adapted to be connected to a potential sufficient to turn on the MOS transistor connected to the middle node of the voltage divider causing it to have a low impedance between its source and drain nodes.

4. A variable delay circuit as claimed in claim 2 wherein a preselected one of said MOS transistors is connected so as to always be turned on whenever the semiconductor memory is operating.

5. A tunable delay circuit for use in creating adjustable delays in integrated circuits comprised of:

a distributed resistance means having capacitance associated therewith for simulating the delay effects found in propagation of signals down delay lines said distributed resistance means being subdivided into a plurality of sections thereby defining nodes between subsections and nodes at either end of said distributed resistance means;

a plurality of switching means having switching terminals, each said switching means having its switching terminals coupling one of said plurality of nodes to a common node at one end of said distributed resistance means where each said switching means has a high impedance state and a low impedance state and each said switching means has a control terminal for controlling the state of each said switching means;

a means for coupling to each said control terminal for controlling whether each said switching device is in a high or low impedance state.

16. A semiconductor memory as defined in claim 5 wherein the characteristics of said first and second voltage sources are selected such that only a predetermined one of said switching means is in said low impedance state at any particular time.

6. A variable delay circuit for optimizing emulation of word line delays in semiconductor memories having distributed resistance word lines, sense amplifiers, and address decoding means comprised of:

a distributed impedance means divided into a plurality of impedance sections and having all said sections connected together to form a series elecrical path through said distributed impedance where the intersections of said impedance sections define a plurality of nodes, said distributed impedance means being coupled between said address decoding means and said sense amplifiers to delay a signal from said address decoding means indicating that an access to said semiconductor memory has commenced and to apply said signal to said sense amplifier after said delay to enable said sense amplifier to sense the data accessed from the selected address;

a plurality of switching means each coupled between one of said plurality of nodes and a common node at one end of said series electrical path where each said switching means has a high impedance state and a low impedance state and each said switching means has a control terminal for controlling the state of each said switching means;

a means for coupling to each said control terminal for controlling whether each said switching device is in a high or low impedance state.

7. A semiconductor memory as defined in claim 6 wherein said distributed impedance means is comprised of a doped polycrystalline semiconductive material deposited over an insulating material on a monocrystalline substrate.

8. A semiconductor memory as defined in claim 6 or 7 wherein each said switching means is an MOS transistor having its drain and source coupled between one of said plurality of nodes to said common node, and having its gate terminal as said control terminal.

9. A semiconductor memory as defined in claim 8 further comprising a plurality of resistive voltage divides each comprised of a first resistor having its first terminal for coupling to a first voltage source and its second terminals coupled to one of said control terminals and a second resistor having a first terminal coupled to said control terminal that said second terminal of said first resistor is coupled to, and said second resistor having a second terminal for coupling to a second voltage source.

10. A semiconductor memory as defined in claim 7 wherein the characteristics of said first and second voltage sources are selected such that only a predetermined one of said switching means is in said low impedance state at any particular time.

11. A method for optimizing emulating of word line delays in semiconductor memories characterized in:

dividing a distributed resistive delay circuit into a plurality of sections each section defining a node;

bypassing combinations of one or more sections with switching devices capable of assuming high and low impedance states between their switching terminals;

storing a predetermined data pattern in the memory;

accessing the memory cells in the semiconductor memory experiencing the longest delays in access time while simultaneously placing one of the switching devices in a low impedance state;

testing the output from the semiconductor memory to determine if a correct access has been made;

if a correct access has been made, selecting another switching device bypassing one or more additional sections than the last switching device selected and causing it to assume a low impedance state while all the other switching devices are in a high impedance state;

testing the output of the semiconductor to determine if a correct access has been made;

repeating the next above two steps until the switching device is found which causes the semiconductor memory to fail to function correctly;

selecting the existing switching device that bypasses the next fewer number of sections of the distributed resistance delay circuit than the switching device that caused failure;

adapting the switching device selected in the step next above to remain permanently in the low impedance state when the semiconductor memory is operating.

12. An integrated circuit semiconductor memory that can be tuned to eliminate extra access time caused by internal access delays comprised of:

an address buffer means (10) for receiving address data on address bus (11) and for generating buffered address data at a first output (14) and for generating a SAT signal at a second output (26) for indicating that an access of said semiconductor memory has begun;

a clock timing means (28) coupled to said second output (26) for receiving said SAT signal and generating a FETCH signal at a first output (29) after receiving SAT, said FETCH signal for starting internal access by said semiconductor memory of the memory cell having the address represented by said buffered address data, and for generating a TIMEOUT signal at a second output (31) for signalling the start of a tunable delay period;

a row decoder means (12) coupled to said first output (14) of said address buffer means (10) to received said buffered address data and coupled to said first output of said clock timing means (28) for receiving said FETCH signal for decoding said buffered address data upon receipt of said FETCH signal and for selecting one of a plurality of output lines and causing it to assume a predetermined electrical state;

a plurality of memory cell means arranged in an array of rows and columns for storing data;

a plurality of distributed resistance word line means (16) coupled to said plurality of output lines from said row decoder means (12), each said word line coupled to a row of said memory cell means including the memory cells in the row connected to said selected word line to be available for access;

a plurality of bit lines (20) each bit line coupled to all the memory cells in a column of said array for coupling to the storage nodes of said memory cell in the row of each column which is selected by said row decoder means (12);

a plurality of sense amplifier means (22) coupled to said bit lines (20) and having an input (34) for receiving a signal indicating that the data on said bit lines (20) is valid regardless of which column and row has been accessed, said sense amplifier means (22) for sensing what data was stored in said accessed memory cell and so indicating and having an output (36);

a tunable delay means (30) coupled to said second output (31) of said clock timing means (28) and having an output (32) for emulating the delay in propagation of the select signal on said word line means (16) by delaying the propagation of said TIMEOUT circuit through said delay means (30) to said output (32) by a tunable amount, said tunable delay means being responsive to electrical signals to thereby provide tunable delay times;

a sense amp clock means (24) coupled to said output (32) of said tunable delay means (30) and to said input (34) of said sense amplifier means (22) for sensing when said TIMEOUT signal has reached a predetermined level at said output (32) and for signalling said sense amplifier means (22) to read the accessed data and to present the data so read at an output (36);

a distributed impedance means divided into a plurality of impedance sections and having all said sections connected together to form a series electrical path from said second output (31) of said clock timing means (28) to said output (32) with the intersection of said impedance sections defining a plurality of nodes;

a plurality of switching means each coupled between one of said plurality of nodes and a common node at one end of said series electrical path where each said switching means has a high impedance state and a low impedance state and each said switching means has a control terminal for controlling the state of each said switching means; and

a means for coupling to each said control terminal for controlling whether each said switching device is in a high or a low impedance state.

13. A semiconductor memory as defined in claim 12 wherein said distributed impedance means is comprised of a doped polycrystalline semiconductive material deposited over an insulating material on a monocrystalline substrate.

14. A semiconductor memory as defined in claim 12 or 13 wherein each said switching means is an MOS transistor having its drain and source coupled between one of said plurality of nodes, and having its gate terminal as said control terminal.

15. A semiconductor memory as defined in claim 14 further comprising a plurality of resistive voltage dividers each comprised of a first resistor having its first terminal for coupling to a first voltage source and its second terminal coupled to one of said control terminals and a second resistor having a first terminal coupled to said control terminal that said second terminal of said first resistor is coupled to, and said second resistor having a second terminal for coupling to a second voltage source.