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Variable delay circuit for emulating word line delay

  • US 4,425,633 A
  • Filed: 10/06/1980
  • Issued: 01/10/1984
  • Est. Priority Date: 10/06/1980
  • Status: Expired due to Term
First Claim
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1. A variable delay circuit for optimizing emulation of word line delays in semiconductor memories having a distributed resistive delay line comprised of:

  • a plurality of nodes interspersed along the length of said distributed resistive delay line and defining a plurality of individual sections of the delay line, and wherein the resistance from each node to a common node at the end of the delay line is a fraction of the total resistance of the entire line;

    a plurality of switching devices with each switching device connected between one of said nodes and common node for bypassing a preselected section or group of sections of the distributed resistive delay time.

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