Multiport programmable digital data set

• US 4,425,664 A
• Filed: 05/07/1982
• Issued: 01/10/1984
• Est. Priority Date: 11/26/1975
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Sherman, David N., Verma, Shiv P.
• Primary Examiner(s): Psitos, Aristotelis M.
• Application Number:
  US06/376,262
• Time in Patent Office: 613 Days
• Field of Search: 375/5, 375/8, 375/9, 178/50, 178/583, 179/15 BA, 179/15 BV, 179/18 ES, 340/147 R, 340/151, 340/152, 340/825
• US Class Current: 375/222
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: H04L 27/0008 arrangements for allowing a transmitter or receiver to use more than one type of modulation negotiating modulation type for two-way transmission paths H04L5/1453

Abstract

Disclosed is a programmable universal data set which is defined as a data set that is capable of simultaneously servicing a plurality of data terminals desiring diverse types of data sets for several different transmission speeds and formats. The universal data set comprises analog and digital buffer processors adapted for interfacing with a plurality of data terminals and with a multi-input transmission medium, a high speed digital processor having a "highly parallel" structure for computing the various elemental functions of the diverse types of data sets, and a cyclic processor for controlling the operational sequence of the high speed processor to achieve the overall operation of the selected types of data sets. The cyclic processor includes means for modifying the types of data sets implemented.

Claims

1. A programmable data modem comprising:

a digital processor,

a plurality of data ports,

a first alterable memory containing a plurality of data set parameters,

a second alterable memory containing a plurality of basic data set implementing operational sequences of instructions, and

control means responsive to said first and second memories for controlling said digital processor simultaneously in accordance with preselected data set parameters and preselected operational sequences to process the various signals at first ones of said ports according to different parameters, and to deliver processed signals to second ones of said ports.

2. Apparatus for transferring data between a plurality of digital data terminals (700) and a transmission medium (800) comprising:

a digital signal processor (200) for performing a plurality of data set functions which collectively implement at least first and second types of data transfer arrangement;

a cyclic processor (100) arranged to store a plurality of sequences of instructions, each of which enable said digital signal processor to perform an associated one of said plurality of functions when said instruction sequence is executed by said processor;

means (300) for sequentially coupling signals originating in each of said data terminals to said digital signal processor for transfer to said transmission medium in accordance with a selected one of said transfer arrangements; and

means (400) for coupling signals from said transmission medium to said digital signal processor for sequential transfer to each of said data terminals in accordance with a selected one of said transfer arrangements.

3. A digital signal processor arranged to interconnect at least one data terminal with a corresponding transmission path, said data terminal arranged to transmit and receive digital information and said transmission path arranged to carry analog signals modulated by digital information, said processor including:

(a) means for modulating said digital information transmitted by said data terminal prior to application to said transmission path, and

(b) means for demodulating said modulated signals to recover said digital information received by said data terminal, CHARACTERIZED IN THAT said modulating and demodulating means includes;

(c) a high-speed digital processor for performing various arithmetic functions on said signals, and

(d) a cyclic processor containing an alterable memory adapted to control the sequence and nature of the operations performed by said high-speed processor in accordance with user defined inputs.

4. A digital data set arranged to (1) modulate an outgoing voice frequency carrier in accordance with first digital signals originating in a data terminal before application to an analog transmission medium path, and to (2) demodulate incoming modulated voice frequency carrier signals received from said transmission medium path to recover second digital signals destined for said data terminal, said data set including:

buffering means for converting signals applied to said data set to a desired digital format,

a high-speed digital processor jointly responsive to said buffering means and a sequence of control signals for sequentially modulating or demodulating applied signals in accordance with a desired modulation or demodulation approach, and

a cyclic processor for generating said control signal sequence in accordance with stored program instructions.

5. A data set including means for modulating and demodulating incoming digital and analog signals respectively in accordance with a plurality of different types of modulation, the type of modulation being dependent upon control signals generated by said data set, and means for selectively providing the control signals corresponding to said plurality of different types of modulation to said modulating and demodulating means whereby simultaneous processing of different types of modulation may be effected.

6. A data set including:

a digital signal processor for performing, in response to stored control signals, operations including modulation, demodulation, filtering and equalization associated with a particular type of data set, and

means for providing said control signals to said digital signal processor to perform said operations in desired sequences on applied signals.

7. The invention defined in claim 6 further including:

first means for coupling said data set to a transmission medium adapted to carry analog modulated signals destined to and generated by said data set, and

second means for coupling said data set to a plurality of terminals adapted to transmit digital signals to and receive digital signals from said data set.

8. The invention defined in claim 7 further including:

means for initiating and terminating communication between ones of said terminals and remote users connected to said transmission medium.

9. A digital signal processor adapted to emulate the functions of at least two different data sets, including:

a high-speed digital processor,

means including a memory for storing at least first and second sets of instructions executable by said high-speed processor, and

means for sequentially applying signal samples derived from first and second data terminals to said high-speed processor whereby said first and second signal samples are sequentially processed in accordance with said first and second sets of instructions.

10. A data set comprising:

a digital buffer processor for coupling said data set to a local data terminal,

an analog buffer processor for coupling said data set to an analog transmission medium,

a high-speed digital signal processor responsive to said analog and digital buffer processors, for modulating signals received in said data set from said local terminal and destined for said transmission medium and for demodulating signals received in said data set from said transmission medium and destined for said data terminal, and

a low-speed cyclical processor for controlling the modulation and demodulation performed by said high-speed processor in accordance with a predefined sequence of stored instructions.

11. A universal data set (FIGS. 1 and 4) for two-way exchange of digital information between a plurality of data communications terminals (700) and remote terminals connected to said data set via an analog transmission medium (800) employing carrier signal waves and having at least as many channels as there are data terminals comprising:

a digital buffer processor (300) connected to and interacting with one or more of said terminals (700) for storing samples of digital data signals in the alternative incoming to or outgoing from one or more of said terminals (700);

an analog buffer processor (400) connected to said transmission medium (800) for converting in the alternative digitally processed outgoing data signals into analog form and analog incoming data signals into digital samples;

a digital processor (200) responsive to buffered samples of outgoing data signals from said terminals (700) and to digitized analog signals from individual channels in said medium (800) for modulating a carrier signal in accordance with outgoing data signals and for demodulating a modulated carrier signal to recover signals incoming from channels in said medium; and

a cyclic processor (100) for storing predetermined program instructions for controlling the sequencing of said digital processor (200) to effect one or more modulation or demodulation formats;

said digital processor (200) further comprising first (210) and second (220) bus lines;

an arithmetic logic unit (230) bridging said bus lines (210,

     220) for performing additive and logic operations on signals appearing on said bus lines and delivering the result to one or the other of said bus lines under the control of said cyclic processor (100); and

memory means (250,

     260) bridging said bus lines (210,

     220) for storing intermediate results of mathematical and logic operations of said arithmetic logic (230) and multiplier (240) units on said signal samples.