Data encoding and decoding communication system for three frequency FSK modulation and method therefor
First Claim
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1. A system for the communication of a sequence of bits of data in the form of Q-ary symbol signals along a plurality of channels comprising:
- a transmitter having means for serially encoding into the Q-ary symbol signal and transmitting the Q-ary symbol signals along the plurality of channels such that at least one of the plurality of channels is devoted to transmitting a Q-ary symbol in place of every second Q-ary symbol from the beginning of a string of repeated Q-ary symbols such that no two Q-ary symbols in succession are transmitted along the same channel; and
a receiver being responsive to said transmitter, having means for serially receiving and decoding said Q-ary symbol signals to reconstruct the sequence of bits of data, and being triggered by transmitting a Q-ary symbol signal along said at least one channel devoted to transmitting every second Q-ary symbol from the beginning of a string of repeated Q-ary symbols to repeat output of a preceding Q-ary symbol.
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Abstract
A system for three frequency FSK modulation wherein binary data bits are sequentially encoded into a ternary system of channels designated "1", "0" and "C", so that a data bit is encoded and transmitted in a "C" channel whenever it is the same as the previous data bit and wherein a transmission in the "C" channel is decoded as a continuation of the previous data bit. The data clock is recovered from the data stream at the transition between data bits and repeated data bits are detected as errors.
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Citations
15 Claims
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1. A system for the communication of a sequence of bits of data in the form of Q-ary symbol signals along a plurality of channels comprising:
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a transmitter having means for serially encoding into the Q-ary symbol signal and transmitting the Q-ary symbol signals along the plurality of channels such that at least one of the plurality of channels is devoted to transmitting a Q-ary symbol in place of every second Q-ary symbol from the beginning of a string of repeated Q-ary symbols such that no two Q-ary symbols in succession are transmitted along the same channel; and a receiver being responsive to said transmitter, having means for serially receiving and decoding said Q-ary symbol signals to reconstruct the sequence of bits of data, and being triggered by transmitting a Q-ary symbol signal along said at least one channel devoted to transmitting every second Q-ary symbol from the beginning of a string of repeated Q-ary symbols to repeat output of a preceding Q-ary symbol.
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2. A transmitter for the encoded transmission of a sequence of bits of data in the form of Q-ary symbol signals along a plurality of channels comprising:
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means for encoding the bits of data into the Q-ary symbol signals such that every second bit from the beginning of a sequence of repeated bits is encoded in at least one of the plurality of channels said at least one of the plurality of channels being devoted to the transmitting a Q-ary symbol in place of repeated Q-ary symbols, having a data input, having a data clock input, and having a plurality of outputs; means for providing access to the plurality of channels having a plurality of inputs coupled to said plurality of outputs of said means for encoding, and having at least one output; and means for transmitting signals along the plurality of channels having at least one input coupled to said at least one output of said means for providing access to a plurality of channels.
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3. A receiver for the reception of a sequence of bits of data in the form of Q-ary symbol signals along a plurality of channels at least one of the plurality of channels being devoted to the transmitting of a Q-ary symbol in place of repeated Q-ary symbols comprising:
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means for receiving signals along the plurality of channels having at least one output; and means for decoding the Q-ary symbol signals transmitted along the plurality of channels such that a Q-ary symbol signal transmitted along the at least one of the plurality of channels devoted to the transmitting of a Q-ary symbol in place of repeated Q-ary symbols is decoded as a repetition of the previous Q-ary symbol.
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4. An encoder for encoded transmission of a sequence of bits of data along a plurality of channels comprising:
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a data clock input; a data input; means for encoding the sequence of bits of data into Q-ary symbol signals such that every second Q-ary symbol from the beginning of a sequence of Q-ary symbols is transmitted in at least one of the plurality of channels, said at least one of the plurality of channels being devoted to the transmitting of a Q-ary symbol in place of repeated Q-ary symbols, said means for encoding the bits of data having a first input coupled to said data clock input, having a second input coupled to said data input, and having a plurality of outputs; and a plurality of switching outputs coupled to said plurality of outputs of said means for encoding the bits of data. - View Dependent Claims (5)
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6. A decoder for use in the reception of encoded transmission of a sequence of bits of data as Q-ary symbol signals, clocked by a data clock along a plurality of channels, at least one of the plurality of channels being devoted to the transmitting a Q-ary symbol in place of repeated Q-ary symbols comprising:
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a plurality of channel inputs; means for comparing the signals along the plurality of channels having a plurality of inputs coupled to said plurality of channel inputs, and having a plurality of outputs; logic means coupled to the plurality of outputs of said means for comparing, for decoding Q-ary symbol signals transmitted in the plurality of channels such that a Q-ary symbol encoded in the at least one of the plurality of channels devoted to the transmitting of a Q-ary symbol in place of repeated Q-ary symbols is decoded as a repetition of the previous Q-ary symbol; and means coupled to said logic means for providing a data output. - View Dependent Claims (7, 8, 9, 10)
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11. A decoder for use in the reception of encoded transmission of a sequence of bits of data as Q-ary symbol signals, clocked by a data clock, along a plurality of channels, at least one of the channels being devoted to transmitting a Q-ary symbol in place of repeated Q-ary symbols, comprising:
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a plurality of channel inputs; a first detector having an input coupled to a first of said plurality of channel inputs and having an output; a second detector having an input coupled to a second of said plurality of channel inputs and having an output; a third detector having an input coupled to a third of said plurality of channel inputs and having an output; a first multiplier having a first input coupled to said output of said first detector, having a second input coupled to said output of said second detector and having an output; a second multiplier having a first input coupled to said output of said first detector, having a second input coupled to said output of said third detector, and having an output; a third multiplier having a first input coupled to said output of said second detector, having a second input coupled to said output of said third detector, and having an output; a means for summing having a first input coupled to said output of said first multiplier, having a second input coupled to said output of said second multiplier, having a third input coupled to said output of said third multiplier, and having an output; a phase-locked loop having an input coupled to said output of said means for summing and having a data clock output; a first filter having a first input coupled to said output of said first detector, having a second input coupled to said data clock output, and having an output; a second filter having a first input coupled to said output of said second detector, having a second input coupled to said data clock output, and having an output; a third filter having a first input coupled to said output of said third detector, having a second input coupled to said data clock output, and having an output; a first comparator having a first input coupled to said output of said first filter, having a second input coupled to said output of said second filter, and having an output; a second comparator having a first input coupled to said output of said first filter, having a second input coupled to said output of said third filter, and having an output; a third comparator having a first input coupled to said output of said second filter, having a second output coupled to said output of said third filter and having an output; a first logic gate having a first input coupled to said output of said first comparator, having a second input coupled to said output of said second comparator, and having an output; a second logic gate having a first input coupled to said output of said third comparator, having a second input and having an output; a third logic gate having a first input coupled to said output of said first logic gate, having a second input coupled to said output of said second logic gate, and having an output; and a first flip-flop having a first input coupled to said output of said third logic gate, having a second input coupled to said data clock output and having an output indicative of the sequence data bits coupled to said second input of said second logic gate. - View Dependent Claims (12)
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13. A method of communicating bits of data in a sequence along a plurality of channels comprising the steps of:
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encoding the sequence of bits of data into a sequence of Q-ary symbol signals and transmitting the Q-ary symbol signals along the plurality of channels such that at least one channel is devoted to the transmission of a Q-ary symbol in place of every second Q-ary symbol from the beginning of a series of successive Q-ary symbols; switching transmission among the plurality of channels between transmission of successive Q-ary symbol signals so that no channel is used for transmission twice in succession; receiving the Q-ary symbol signals along the plurality of channels; and decoding the Q-ary symbol signals into a sequence of bits of data such that the Q-ary symbols are sequenced in the order received and such that reception of a Q-ary symbol signal along said at least one channel devoted to transmission of a Q-ary symbol signal in place of successively repeated Q-ary symbols is used to trigger the output of a repetition of a preceding Q-ary symbol.
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14. A method of recovering a data clock from a plurality of channels having a sequence of bits of data encoded into Q-ary symbols and transmitted as Q-ary symbol signals having overlapping rise and fall times and being ordered such that no channel is used to transmit two Q-ary symbol signals in succession, comprising the steps of:
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multiplying the Q-ary symbol signal levels from the said plurality of channels together in all combinations; and summing the results of said multiplying step to generate pulses indicative of the data clock.
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15. A method for detecting errors in the Q-ary symbol signals along a plurality of channels containing a sequence of bits of data encoded into Q-ary symbols such that no channel is used to transmit two Q-ary symbols in succession, comprising the steps of:
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comparing the present Q-ary symbol signal level with the previous Q-ary symbol signal level in the same channel; and providing an output signal indicative of an error whenever any two Q-ary symbol signals are received along any channel in succession.
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Specification