Memory system having an alternate memory

• US 4,426,688 A
• Filed: 08/03/1981
• Issued: 01/17/1984
• Est. Priority Date: 08/03/1981
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Moxley, David C.
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US06/289,640
• Time in Patent Office: 897 Days
• Field of Search: 365/200
• US Class Current: 365/200
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A memory system having both a primary memory and an alternate memory. The alternate memory stores data to be substituted for data stored at memory locations in the primary memory that have defective cells. The alternate memory includes a byte memory and a bit memory. The byte memory stores bytes of data that are to replace bytes having multiple bit errors in the primary memory. The bit memory stores bits to replace single bits in any byte in the primary memory that has a single bit error. A mapping memory controls access to the primary memory and the alternate memory. The memory devices in the primary memory have either all row defects or all column defects in order to reduce the size of the mapping memory.

Claims

1. A memory system, comprising:

a primary memory having a plurality of addressable memory locations each of which has memory cells for storing a primary group of data bits, with some of the memory cells of the primary memory being defective;

an alternate memory for storing replacement data bits to replace any data bits stored in said primary memory at locations having a defective memory cell, said alternate memory including a first alternate memory portion having a plurality of addressable memory locations each of which is for storing a first alternate group of bits, and a second alternate memory portion having a plurality of addressable memory locations each of which is for storing second alternate groups of bits, where each first alternate group of bits consists of a first predetermined number of bits and each second alternate group of bits consists of a second predetermined number of bits, and where said first predetermined number is greater than said second predetermined number; and

means for replacing bits in the primary groups of bits read from locations in said primary memory having a defective memory cell with bits from the first and second alternate groups of bits, so that bits in the primary groups from locations having more than said second predetermined number of defective bit cells are replaced with bits from the first alternate groups of bits and bits in the primary groups from other locations having defective bit cells are replaced with bits from the second alternate groups of bits.

2. The memory system of claim 1, wherein each said second alternate group is a single bit, and wherein said means for replacing comprises means for replacing a single bit in any primary group read from a location having a single defective memory cell with one said second alternate group.

3. The memory system of claim 2, wherein each location of said primary memory stores a byte of data bits, wherein each first alternate group of bits is a byte of data, and wherein said means for replacing further comprises means for replacing the entire primary group of bits from any location in said primary memory having multiple defective memory cells with one of said first alternate groups of bits.

4. The memory system of claim 3, wherein said memory system further comprises a mapping memory for storing bits associated with each of said locations in said primary memory having at least one defective memory cell for addressing one of said first and second alternate memory portions for replacing bits in the primary group of data bits stored at the location having at least one defective memory cell.

5. The memory system of claim 4, wherein said means for replacing the bits in the primary group of bits from said location having a single defective memory cell comprises a bit substitution circuit for receiving the primary group of bits having the single defective memory cell from said primary memory and for receiving the bit of one of said second groups of bits from said second alternate memory portion, and for substituting the bit in the primary group stored at the defective memory cell with the bit from said second alternate memory portion.

6. The memory system of claim 3, wherein said means for replacing includes a mapping memory for storing control bits associated with each of said locations having at least one defective memory cell, wherein said primary memory includes a plurality of memory devices for each storing a single bit at a location defined by addressable rows and columns, with each memory device having defective memory cells that are either in all the memory cells in any one of the columns or in all of the memory cells in any one of the rows, so that the alternate memory may be addressed by the control bits from said mapping memory and a portion of the address bits used to address one of the locations in said primary memory.

7. In a data processing system having a primary memory with a plurality of addressable memory locations, each memory location for storing a primary group of data bits, and an alternate memory for storing data bits to replace data bits in the primary groups of data bits of said primary memory that are stored in said primary locations having defective memory cells, the improvement wherein said alternate memory comprises:

a first alternate memory portion for storing data bits in first groups; and

a second alternate memory portion for storing data bits in second groups, each of said second groups having at least one bit but having a number of bits less than the number of bits in each said first group, so that said first groups are used to replace bits in those primary groups of bits stored at each location having a greater number of defective memory cells than the number of data bits in any of said second groups, and so that said second groups are used to replace bits in those primary groups of bits stored at locations having a number of defective memory cells which is the same or less than the number of data bits in any of said second groups.

8. A memory system, comprising:

a primary memory having a plurality of addressable locations, each location for storing a primary group of data bits, with at least some of said locations having at least one defective memory cell;

an alternate memory for storing replacement data bits for any primary group of data bits stored in said primary memory at said locations having a defective memory cell, said alternate memory including a first alternate memory portion for storing first alternate groups of bits and a second alternate memory portion for storing second alternate groups of bits, with each of the first alternate groups having a first predetermined number of bits and each of the second alternate groups of bits having a second predetermined number of bits less than the first predetermined number; and

means for replacing bits in the primary groups of bits read from said locations in said primary memory having defective memory cells with the second alternate groups of bits when said locations have the same or a lesser number of defective cells than the second predetermined number, and replacing the bits in the primary groups of bits read from said locations in said primary memory having defective cells with the first alternate groups of bits when said locations have a number of defective cells greater than the second predetermined number.

9. The memory system of claim 8, wherein the primary number of bits in each primary group is the same as the first predetermined number in the first alternate group, so that when the number of defective cells is greater than the second predetermined number, all of the bits in the primary group are replaced.

10. The memory system of claim 9 wherein each location of said primary memory stores a byte of data bits, wherein the first predetermined number of bits in each of the first alternate groups is a byte of data bits, and wherein the second predetermined number of bits in each of the second alternate groups is a single bit.

11. In a memory system of the type having a primary memory with a plurality of memory devices, each memory device having data bits stored at memory cells in addressable rows and columns, and with at least some of the memory devices having defective memory cells, having an alternate memory for storing data bits to be substituted for the data bits stored at the defective memory cells in the primary memory, and having a mapping memory for storing control bits to address one or more bits in the alternate memory that are to replace the bits stored at defective memory cells in the primary memory, the improvement wherein each memory device at said primary memory has defective memory cells that are either in all of the memory cells in any one of the addressable columns of in all of the memory cells in any one of the addressable rows, so that only a portion of the bits needed to address the alternate memory comes from the mapping memory, with the remaining number of bits needed to address the alternate memory coming from the address bits used to address the primary memory.

12. A method for reducing the amount of memory space needed in an alternate memory to store data bits used to replace data bits stored at defective memory cells in an associated primary memory, the method comprising:

providing a byte memory in said alternate memory, said byte memory having a plurality of addressable locations for each storing a byte of data;

providing a bit memory in said alternate memory, said bit memory having a plurality of addressable locations each storing a single bit; and

replacing the bits stored at locations in the primary memory having defective memory cells so that when multiple bits in each byte from the primary memory are stored at defective cells, the entire byte from the primary memory is replaced by a byte from the byte memory, and when only a single bit from a byte at the primary memory is stored at a defective memory cell, only the single bit is replaced by a bit from the bit memory.