Bus system with address and status conductors

• US 4,426,697 A
• Filed: 06/24/1981
• Issued: 01/17/1984
• Est. Priority Date: 06/26/1980
• Status: Expired due to Fees

• Current Assignee: Diehl GmbH & Co. KG
• Original Assignee: Diehl GmbH & Co. KG
• Inventors: Petersen, Hans, Stegmann, Kurt
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/276,915
• Time in Patent Office: 937 Days
• Field of Search: 370/85, 370/91, 370/92, 370/67, 370/86, 340/825.05, 340/825.06, 340/825.07, 340/825.08, 340/825.52
• US Class Current: 370/438
• CPC Class Codes: H04M 9/025 Time division multiplex systems, e.g. loop systems

Abstract

A bus system with an address conductor and a status conductor onto which there are connected mutually parallel stations with programmable address decoders and with status decoders and/or status encoders, whereby the address conductor carries a sequence of address informations and the status conductor status informations timewise associated therewith. The bus system is essentially so constructed whereby the address conductor carries mutually spaced serially binary coded bit patterns of presently m address bits (address-bit pattern m), and the status conductor which is displaced relative to the address-bit pattern carries a serial bit pattern of r status bits (status-bit pattern r).

Claims

1. In a bus system including an address conductor and a status conductor;

mutually parallel stations having programmable address decoders, status decoders and status encoders connected to said conductors, said address conductor carrying a sequence of address informations and said status conductor carrying status informations timewise associated therewith;

the improvement comprising;

said address conductor carrying mutually spaced, serially binary coded bit patterns of, respectively, m-address bits; and

said status conductor carrying a serialized bit pattern of r-status bits offset relative to the address bit pattern m.

2. Bus system as claimed in claim 1, wherein predetermined bits of said status bit pattern r are fixedly associated to predetermined status and/or address informations.

3. Bus system as claimed in claim 1 or 2, comprising a readiness bit pattern n ahead of said address bit pattern m;

and a readiness bit pattern v ahead of said status bit pattern r whereby at predetermined stations there is initiated the detection of the readiness bit pattern v from the readiness bit pattern n.

4. Bus system as claimed in claim 3, wherein in said predetermined stations there is initiated the reading in of parallel-series converted status informations from an encoder into the status conductor from an address decoder.

5. Bus system as claimed in claim 1, comprising a fixedly preset readiness bit pattern n ahead of the address bit pattern m.

6. Bus system as claimed in claim 1, comprising a waiting bit pattern a in the form of a constant L-potential given on the address conductor between the end of an address bit pattern m and the start of the following readiness bit pattern n.

7. Bus system as claimed in claim 1, comprising a series-parallel conversion for the decoding of the address information (a) and the status information s, which is automatically controlled through a lead bit directly ahead of the address bit pattern m or the status bit pattern r.

8. Bus system as claimed in claim 1, wherein said address conductor carries an address bit pattern related to the sequence of all possible status bit patterns v presently separated by a readiness bit pattern n, and said status conductor therefrom carries only those of the status bit pattern r which is connected from the status transmitter activated by its address decoding to the status conductor.

9. Bus system as claimed in claim 1 comprising a bistable switch element between a current status transmitter, as present in at least one of said parallel stations, and the output of the status decoder associated with said status transmitter, which is resettable from a readiness decoder connected to the address conductor.

10. Bus system as claimed in claim 1, comprising a bistable switch element between a current status signal transmitter, as present in at least one of said parallel stations, and the output of a status decoder associated with said status signal transmitter, which is resettable from a decoder supplied from the address conductor and interrogated by address bit pattern is not associated with this status signal transmitter.

11. Bus system as claimed in claim 1, comprising stations, speaker locations and signal storages forming a communication system for the crew of a commercial jumbo aircraft, and a status transmitter, as present in at least one of said parallel stations, comprises cradle switches and call buttons at speaker locations and storages.