Data communications network

• US 4,428,043 A
• Filed: 08/24/1981
• Issued: 01/24/1984
• Est. Priority Date: 08/24/1981
• Status: Expired due to Term

• Current Assignee: Burroughs Corp (Unisys Corporation)
• Original Assignee: Burroughs Corp (Unisys Corporation)
• Inventors: Harris, Craig W., Catiller, Robert D., Mathews, Ronald D.
• Primary Examiner(s): Atkinson, Charles E.
• Assistant Examiner(s): Lee, Jameson
• Application Number:
  US06/295,587
• Time in Patent Office: 883 Days
• Field of Search: 364/200, 364/900, 361/391, 361/397
• US Class Current: 709/250
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

Base connection modules are used to house slide-in cards which form a Network Support Processor which executes data transfer operations for up to four main host computers. One Network Support Processor can control up to four Line Support Processors, each one of which manages up to 16 Line Adapters connected, via data communication lines, to remote terminals. The line Support Processor, via its Line Adapters, handles a wide variety of communication line disciplines but provides a common discipline to its Network Support Processor and the host computer.

Claims

1. A data communications network comprising:

(a) a main host computer having a main processor and main memory, said host computer communicating via a first bus (MLI) means to a base connection module;

(a1) said first bus means for carrying data and control signals between said main host computer and a network support processor-controller via a first Distribution control circuit unit;

(b) said base connection module for housing and interconnecting a plurality of circuit units, said plurality of circuit units forming an I/O subsystem which includes;

(b1) said first Distribution control circuit unit which includes means responsive to requests from said main host computer and/or said network support processor-controller, for connecting said network support processor-controller to said main host computer for data transfer operations therebetween, and for disconnecting said main host computer from said network support processor-controller when said processor-controller is occupied in transferring data to/from a line communications processor;

(b2) a second Distribution control circuit unit which includes means, responsive to requests from said network support processor-controller and/or said line communications processor, for connecting said processor-controller to said line communications processor for data transfer operations therebetween, and for disconnecting said processor-controller from said line communications processor when said processor-controller is occupied in transferring data to/from said main host computer;

(b3) said network support processor-controller connected to said first and second Distribution control circuit units and functioning to execute data transfers between said main host computer and said line communications processor via a shared memory means, shared by a first and a second processor means said network support processor-controller including;

(b3-a) an Interface circuit unit connecting a master processor means and a master memory controller to said first and second Distribution control circuit units, said Interface circuit operating under control of said master processor means, and which includes;

(b3-a1) means for synchronous data transfer to/from said first Distribution control circuit unit;

(b3-a2) means for asynchronous data transfer to/from said second Distribution control circuit unit;

(b3-b) master processor-controller means including;

(b3-b1) said first processor means for generating instructions and control signals for operation of said Interface circuit unit and for operation of a slave processor-controller means;

(b3-b2) a first memory control circuit, connected to said first processor means and including;

(b3-b2a) first memory means for storing instructions and data for said first processor means;

(b3-b2b) first memory logic means for generating addresses to access a shared memory means;

(b3-c) a slave processor-controller means including;

(b3-c1) said second processor means for accessing data in said shared memory means and including;

(i) means to edit and manipulate protocol format of data from said shared memory means;

(ii) means to return processed data back to said shared memory means;

(iii) means to transfer said processed data, under instructions from said first processor means, to said first or second Distribution control circuit means via said Interface circuit unit;

(b3-c2) a second memory control circuit, connected to said second processor means, and including;

(i) second memory means for storing instructions and data for said second processor means;

(ii) second memory logic means for generating memory addresses to access said shared memory means;

(c) said shared memory means, connected to said first and second memory control circuit and to said Interface circuit for temporary storage of data-in-transit between said host computer and said line communications processor;

(d) said line communications processor connected to said Interface circuit unit via said second Distribution control circuit unit, said line communications processor including;

(i) a plurality of Line Adapters, wherein each Line Adapter services a data communication line to a remote peripheral terminal;

(ii) means to control data transfers between said remote peripheral terminal and said second Distribution control circuit unit.

2. A data communications network comprising:

(a) a plurality of main host computers each connected via its own separate bus to a base connection module means each of said host computers including;

(a1) means to provide first control signals to a selected first distribution control circuit unit to establish connection or disconnection to a network support processor-controller;

(b) said base connection module means for providing a connective backplane for the electrical connection of slide-in connector cards wherein each of said slide-in connector cards house circuitry providing for an I/O subsystem useful for enabling and controlling data transfers between a selected main host computer and a selected line communications processor connected to remote terminals, said base connection module means including;

(b1) a plurality of first distribution control circuit units including said selected first distribution circuit, each of which is connected to one of said plurality of host computers, said first distribution control circuit units including;

(b1-1) means responsive to said first control signals to connect and/or disconnect a selected one of said main host computers to a network support processor-controller, said connection and disconnection being controlled by control signals from said main host computer and/or said network support processor-controller;

(b1-2) means providing asynchronous communication between a selected one of said host computers and a selected one of said first distribution control circuit units;

(b1-3) means providing synchronous communication between a selected one of said first distribution control circuit units and said network support processor-controller;

(b2) means for selection of one of said first plurality of distribution control circuit units for data transmission between a selected main host computer and said network support processor-controller;

(b3) a second distribution control circuit unit connected to said network support processor-controller and to a plurality of line communications processors each of which manage a plurality of communication lines to remote terminals, each said second distribution control circuit units including;

(b3-1) means providing asynchronous communication between itself and said network support processor-controller; and

(b3-2) means providing synchronous communication between itself and said line communications processors;

(b3-3) means for selecting an addressed line communications processor;

(b3-4) means, responsive to second control signals from a line communications processor, for establishing connection and/or disconnection to said network support processor-controller;

(b4) said network support processor-controller connected to a selected host computer of said plurality of host computers via a selected distribution control circuit unit, said network support processor-controller operating to receive basic data transfer commands from said selected main host computer and to execute said data transfer commands without further attention from said main host computer, said network support processor-controller including;

(b4-a) a first processor-controller means for controlling data transfers to/from a shared memory means to/from said main host computer and said line communications processor, said first processor controller means including;

(b4-a1) a first processor means operating to provide instruction to an interface circuit means and a first memory controller;

(b4-a2) said first memory controller for placing data into and accessing data from said shared memory means;

(b4-b) a second processor-controller means initiated by said first processor means, said second processor-controller means including;

(b4-b1) a second processor means for editing and for protocol management of data placed in said shared memory means during transfer to/from said line communications processor and said host computer, said second processor means further including;

(b4-b1a) means for providing instructions to a second memory controller;

(b4-b2) said second memory-controller for accessing data from said shared memory means to be processed by said second processor means, and for placing processed data back into said shared memory means for subsequent access by said first processor-controller means;

(b4-c) an interface circuit means, initiated by said first processor means, and including;

(i) means for providing synchronous communication to a selected one of said first distribution control circuit units for transfer to said selected main host computer; and

(ii) means for providing asynchronous communication to said second distribution control circuit units for communication with a selected line communications processor;

(b4-d) said shared memory means connected to said first and second memory controller, said memory means operating to store data being transferred until such data can be processed by said second processor means;

(c) a plurality of line communications processors connected selectively to one of said second distribution control circuit units, each of said line communications processors including;

(c1) processor means for controlling a plurality of line adapters for the selection of a line adapter and the initiation of data transmissions to and from a remote terminal unit, and to and from said network support processor via said second distribution control circuit unit;

(c2) a plurality of line adapters controlled and selected by said processor means where each of said line adapters includes;

(c2-1) means to time data transmission to and from a remote terminal unit to match the acceptable transfer rate of said terminal unit;

(c2-2) means to serialize bit information from/to byte information;

(c3) means to provide second control signals to said second distribution control circuit unit to establish connection or disconnection to said network support processor-controller.

3. A data communication network comprising:

(a) a main host computer including a main processor and main memory, said host computer connected to a first connection circuit means via a first message level interface bus means;

said main host computer including;

(a1) means to generate a poll request command to said first connection circuit means for establishing a data transfer connection to a remote terminal, said poll request command including address data for selecting said remote terminal;

(a2) means to generate address data for selecting a remote terminal unit connected to a selected line communication processor;

(b) said first connection circuit means for connecting and disconnecting said main host computer to/from a network support processor, said first connection circuit means including;

(b1) means for executing asynchronous data transfers between said host computer and said first connection circuit means via said first message level interface bus means;

(b2) means for executing synchronous data transfers between said first connection circuit means and said network support processor over a first data link interface bus means;

(b3) means for connecting and disconnecting said network support processor with said main host computer;

(b4) said first connection circuit means operating in response to (i) a "poll request" command from said main host computer requesting connection for data transfer between a remote terminal having a data communication line to a line communication processor, or operating in response to (ii) a "poll test" command from said network support processor requesting connection to said main host computer for data transfers from said line communication processor to said main host computer;

(c) said first message level interface bus means connecting said main host computer to said first connection circuit means;

(d) said first data link interface bus means connecting said first connection means to said network support processor;

(e) a network support processor for executing synchronous data transfers to/from said first connection circuit means via said first data link interface bus means, and for executing asynchronous data transfers to/from a second connection circuit means via a second message level interface bus means;

said network support processor including;

(e1) means to generate a "poll test" command to said first connection circuit means to establish a data transfer connection to said host computer;

(e2) means to generate a "poll request" command to a second connection circuit means to establish a data transfer connection to a line communications processor;

(f) second message level interface bus means connecting said network support processor to a second connection circuit means;

(g) second connection circuit means for connecting and disconnecting said network support processor to said line communication processor, said second connection means including;

(g1) means for executing asynchronous data transfers between said network support processor and said second connection circuit means;

(g2) means for executing synchronous data transfers between said second connection means and said line communication processor;

(g3) means for connecting and disconnecting said network support processor with said line communication processor in response to a "poll request" command from said network support processor or a "poll test" command from said line communication processor;

(h) said second data link interface bus means connecting said second connection circuit means to said line communication processor;

(i) said line communication processor for routing data between a remote terminal, connected to said line communication processor, and said second connection circuit means, said line communication processor including;

(i1) means to read address data received from said main host computer and to connect a selected remote terminal, according to said address data, for data transfer operations;

(i2) a plurality of data communication lines, each line connecting to a remote terminal;

(j) a plurality of remote terminals connected to said line communication processor wherein each terminal is selectively addressable by said line communication processor.