Process for the manufacture of vertical P-N junctions in the pulling of silicon from a silicon melt

• US 4,428,783 A
• Filed: 12/14/1981
• Issued: 01/31/1984
• Est. Priority Date: 12/29/1980
• Status: Expired due to Fees

• Current Assignee: Heliotronic Forschungs- und Entwicklungsgesellschaft Fur Solarzellen-Grundstoffe mbH
• Original Assignee: Heliotronic Forschungs- und Entwicklungsgesellschaft Fur Solarzellen-Grundstoffe mbH
• Inventors: Gessert, Cord
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US06/330,331
• Time in Patent Office: 778 Days
• Field of Search: 148/171, 148/187, 148/172, 148/173, 29/572, 29/576 E, 156/617 SP
• US Class Current: 117/22
• CPC Class Codes: C30B 15/20 Controlling or regulating controlling or regulating in general G05

Abstract

The invention makes it possible to manufacture silicon wafers having vertical p-n junctions as the basic material for solar cells. As a result of simultaneously adding certain dopants that act in the silicon crystal as donors and certain dopants that develop acceptor properties and also as a result of measures that result in a periodic change in the crystal growth from a low rate v_n to a high rate v_n, p- and n-conductive zones are produced in the silicon, each having a total length of from 5 to 2000 μm.

Claims

1. In a process for the manufacture of p-n junctions in the pulling of silicon ribbons, polygons or tubes from a silicon melt, the improvement comprising:

adding to the silicon melt both dopants that act as acceptors and dopants that act as donors, of which the effective distribution coefficients k_Aeff (v_h) and k_Deff (v_h) at a high crystal growht rate v_h and the effective distribution coefficients k_Aeff (v_h) and k_Deff (v_h) at a low crystal growth rate v_n satisfy the condition ##EQU9## wherein, generally, v_h is a crystal growth rate higher than the mean pulling speed and v_n is a crystal growth rate lower than the mean pulling speed;

pulling silicon from the melt at a mean pulling speed of from 6 to 120 mm/min.; and

periodically varying the crystal growth rate during the pulling operation between a low rate v_n and a high rate v_h so that the total length of each p- and n-conductive zone in the crystallized silicon is from 5 to 2000 μ

m.

2. The process according to claim 1, wherein said dopants comprise dopant pairs so selected as to allow a high average pulling speed with a small difference between v_n and v_h.

3. The process according to claim 1, wherein said dopant pairs are selected from the group consisting of boron/bismuth, indium/phosphorus, gallium/phosphorus and aluminum/arsenic.

4. The process according to claim 1, wherein said step of varying the crystal growth rate to effect a periodic change from a low growth rate v_n to a high rate v_h comprises periodically varying the pulling speed.

5. The process according to claim 1, wherein said step of varying the crystal growth rate to effect a periodic change from a low growth rate v_n to a high rate v_h comprises periodically varying the temperature of the melt in the region of the growth front.

6. The process according to claim 1, additionally including the step of arranging the total length l of each p- and n-conductive zone in the crystallized silicon so that it is so related to the diffusion length L_d of the minority carriers in silicon for solar cells as to satisfy the condition

7. The process according to claim 1, wherein the low crystal growth rate v_n is at least 6 mm/min. below the said mean pulling speed and the high crystal growth rate v_h is at least 6 mm/min. above said mean pulling speed.