Data buffer operating in response to computer halt signal

• US 4,429,362 A
• Filed: 06/18/1981
• Issued: 01/31/1984
• Est. Priority Date: 06/18/1981
• Status: Expired due to Fees

• Current Assignee: The Bendix Corporation (Honeywell International Inc.)
• Original Assignee: The Bendix Corporation (Honeywell International Inc.)
• Inventors: Costantini, John J.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Watson, Mark P.
• Application Number:
  US06/275,005
• Time in Patent Office: 957 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/48
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 13/4226 with asynchronous protocol
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A buffer can exchange data between a computer having a plurality of lines and a device. One of these lines, a halt line, can transmit a halt signal when the computer has halted. The buffer includes a plurality of transmitters and a plurality of controlled receivers. A halt transmitter is included among the plurality of transmitters. The transmitters are separately connected to predetermined respective ones of the plurality of lines for transmitting their signals to the device. The halt transmitter is connected to the halt line for transmitting the halt signal to the device. The receivers are connected between the device and given respective ones of the plurality of lines for coupling to them signals from the device. Each one of a predetermined set from the plurality of receivers has a receive terminal commonly connected to the halt line for enabling operation of this predetermined set in response to the halt signal.

Claims

1. A buffer for exchanging data between a device and a computer, the former having means for providing a plurality of device signals, the latter having a plurality of lines including a halt line, said halt line being operable to transmit a halt signal when said computer has halted, said buffer comprising:

a plurality of transmitting means, including a halt transmitter, each separately connected to predetermined respective ones of said plurality of lines, each of said plurality of transmitting means being operable to transmit its signal to said device, said halt transmitter being connected to said halt line for transmitting said halt signal to said device; and

a plurality of receiving means connected between said device and given respective ones of said plurality of lines for coupling to them said device signals from said device, said given respective ones of said lines and said predetermined respective ones of said lines having at least one common member, each one of a predetermined set from said plurality of receiving means having a control means for controlling said predetermined set, said control means having a receive terminal commonly connected to said halt line for enabling operation of said predetermined set in response to said halt signal, the presence and absence of said halt signal on said halt line being effective to enable and disable, respectively, said predetermined set from said plurality of receiving means.

2. A buffer according to claim 1 wherein a first preselected set from said plurality of transmitting means are connected in antiparallel with a first preselected group from said plurality of receiving means, said first preselected set and group being connected to and controlled by said computer to render them alternately operable to allow simplex communication between said device and said computer.

3. A buffer according to claim 2 wherein those of said given respective ones of said lines connecting to said first preselected group comprise address lines for said computer.

4. A buffered test system according to claim 1, 2 or 3 wherein said device is a digital computing device.

5. A buffer according to claim 2 wherein each of said first preselected set includes a transmit terminal commonly connected to said halt line for transmitting in response to said halt signal but at a time different from when said predetermined set is enabled to operate by said halt signal.

6. A buffer according to claim 2 wherein a second preselected set from said plurality of transmitting means are connected in antiparallel with a second preselected group from said plurality of controlled receiving means, said second preselected set and group being connected to and controlled by said computer to render them alternately operable to allow simplex communication.

7. A buffer according to claim 6 wherein those of said given respective ones of said lines connecting to said second preselected group comprise data lines of said computer.

8. A buffer according to claim 7 wherein said plurality of lines includes a plurality of control lines, and wherein a third preselected set from said plurality of transmitting means are connected to a portion of said control lines, the remaining ones of said control lines being connected to a third preselected group from said plurality of controlled receiving means.

9. In a tester having at least one unit to be tested and a remote device for providing a plurality of device signals, a buffered test system for testing said unit with said remote device, comprising:

a test instrument having a test terminal which is connectable to said unit to measure an operating parameter thereof, said test instrument being operable to provide measurement signals;

a computer having a plurality of lines for providing thereon a plurality of signals, at least one of said lines being connected to said test instrument for sending it a signal to commence operation and for receiving from it a measurement signal;

a plurality of transmitting means separately connected to predetermined respective ones of said plurality of lines for transmitting to said device their signals, including one corresponding to said measurement signal; and

a plurality of receiving means connected between said device and given respective ones of said plurality of lines for coupling to them said device signals from said device, said given respective ones of said lines and said predetermined respective ones of said lines having at least one common member, said plurality of lines including a halt line operable to transmit a halt signal when said computer has halted, said plurality of transmitting means including a halt transmitter connected to said halt line for transmitting said halt signal to said device, each of a predetermined set from said plurality of receiving means having a control means for controlling said predetermined set, said control means having a receive terminal commonly connected to said halt line for enabling operation of said predetermined set, the presence and absence of said halt signal on said halt line being effective to enable and disable, respectively, said predetermined set from said plurality of receiving means.

10. A method for exchanging data between a device, a test instrument and a computer having a plurality of lines including a halt line operable to convey a halt signal when said computer has halted, said device being operable to provide device signals, comprising the steps of:

transmitting signals from predetermined respective ones of said plurality of lines to said device;

coupling said device signals from said device to given respective ones of said plurality of lines when a halt signal is provided by said computer on said halt line;

providing onto said plurality of lines a predetermined signal from said computer after the provision of said halt signal;

rendering said test instrument operative when said predetermined signal is provided on said plurality of lines by said computer; and

relaying measurements obtained by said instrument through said plurality of lines.