Authorization mechanism for establishing addressability to information in another address space
First Claim
1. In a multiprogramming data processing system including (1) a main memory comprised of an addressing mechanism providing access to addressable information including data, problem programs, supervisor programs, and system control tables including addressable address translation tables for translating virtual addresses to real main memory addresses and (2) a processor including:
- (a) an instruction counter connected to the addressing mechanism for extracting program instructions from the main memory;
(b) an address translation control register in the processor for storing a main memory address, transferrable by the processor to the main memory addressing mechanism, to provide access to a particular address translation table used for translating addresses of an associated program from virtual to real main memory addresses;
(c) an address space number (ASN) control register for storing a plural-binary-bit present-ASN number providing a symbolic identifier of said particular address translation table addressed by said address translation control register; and
(d) a processor control including program instruction decoding and execution control signal means, register, data path, and gate means connected and responsive to said execution control signal means, a machine implemented process in which said processor is controlled by said processor control in response to a program instruction to perform the method steps of;
transferring from main memory a new-ASN for storage in said ASN control register, and the address of an associated address translation table for storage in said address translation control register;
accessing from main memory a new-ASN-specified entry in a first system control table and transferring said entry to a register of said processor control, said particular entry comprising space switch authority control information including an authority control entry for each ASN that may be designated as a new-ASN indicating if the new-ASN can be used as a primary or secondary address space;
testing said space switch authority control information with an authorization index stored in said processor control, related to the present-ASN, for providing an interrupt signal in the processor if the program instruction associated with the present ASN is not authorized to establish use of the address translation table associated with the new-ASN.
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Abstract
Permits one program in one address space to obtain access to data in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. Addressability to a second address space may be specified by a program if authorized in accordance with the entry of an authority table associated with the second address space, the entry being designated by an authorization index associated with the program.
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Citations
3 Claims
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1. In a multiprogramming data processing system including (1) a main memory comprised of an addressing mechanism providing access to addressable information including data, problem programs, supervisor programs, and system control tables including addressable address translation tables for translating virtual addresses to real main memory addresses and (2) a processor including:
- (a) an instruction counter connected to the addressing mechanism for extracting program instructions from the main memory;
(b) an address translation control register in the processor for storing a main memory address, transferrable by the processor to the main memory addressing mechanism, to provide access to a particular address translation table used for translating addresses of an associated program from virtual to real main memory addresses;
(c) an address space number (ASN) control register for storing a plural-binary-bit present-ASN number providing a symbolic identifier of said particular address translation table addressed by said address translation control register; and
(d) a processor control including program instruction decoding and execution control signal means, register, data path, and gate means connected and responsive to said execution control signal means, a machine implemented process in which said processor is controlled by said processor control in response to a program instruction to perform the method steps of;transferring from main memory a new-ASN for storage in said ASN control register, and the address of an associated address translation table for storage in said address translation control register; accessing from main memory a new-ASN-specified entry in a first system control table and transferring said entry to a register of said processor control, said particular entry comprising space switch authority control information including an authority control entry for each ASN that may be designated as a new-ASN indicating if the new-ASN can be used as a primary or secondary address space; testing said space switch authority control information with an authorization index stored in said processor control, related to the present-ASN, for providing an interrupt signal in the processor if the program instruction associated with the present ASN is not authorized to establish use of the address translation table associated with the new-ASN. - View Dependent Claims (2, 3)
- (a) an instruction counter connected to the addressing mechanism for extracting program instructions from the main memory;
Specification