Dynamic operational amplifier

• US 4,431,971 A
• Filed: 08/17/1981
• Issued: 02/14/1984
• Est. Priority Date: 08/17/1981
• Status: Expired due to Term

• Current Assignee: AMI Semiconductor Inc (ON Semiconductor Corporation)
• Original Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Inventors: Haque, Yusuf A.
• Primary Examiner(s): Mullins, James B.
• Assistant Examiner(s): Wan, Gene
• Application Number:
  US06/293,744
• Time in Patent Office: 911 Days
• Field of Search: 330/253, 330/261, 330/107, 330/296, 330/297, 307/246, 307/355, 307/296 A, 320/1
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45461 the CSC comprising one or more switched capacitors
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence

Abstract

A unique dynamic operational amplifier is constructed utilizing a switched capacitor (25) as the biasing means, wherein the switched capacitor biasing means is capable of effectively doubling the power supply voltage supplied to the dynamic operational amplifier, thus greatly extending the range of the input voltage (V_IN) and output voltage (V_OUT) of the dynamic operational amplifier.

Claims

1. A dynamic operational amplifier comprising:

a first and a second load device, each having first and second leads, said first leads being connected in common to a first power supply lead connected to a first power supply voltage;

an output node connected to said second lead of said second load device;

a non-inverting input transistor having a first lead connected to said second lead of said first load device, a second lead serving as a non-inverting input lead, and a third lead;

an inverting input transistor having a first lead connected to said second lead of said second load device, a second lead serving as the inverting input lead, and a third lead connected in common with said third lead of said inverting input transistor to a second power supply voltage lead;

a capacitor having a first and a second plate;

first switch means connected between said first power supply voltage and said first plate of said capacitor;

second switch means connected between a second power supply voltage and said second plate of said capacitor;

third switch means connected between said second power supply voltage and said first plate of said capacitor;

fourth switch means connected between said second power supply lead and said second plate of said capacitor;

wherein said first and said second switch means are closed and said third and fourth switch means are open during a first clock phase of a two phase non-overlapping clock signal, thereby causing said capacitor to be charged between said first power supply voltage and said second power supply voltage and said first and said second switch means are open and said third and said fourth switch means are closed during a second clock phase of said two phase non-overlapping clock signal, thereby applying the negative of the voltage stored on said capacitor during said first clock phase to said second power supply lead.

2. Structure as in claim 1 further comprising:

a second capacitor having a first and a second plate;

fifth switch means connected between said first power supply voltage and said first plate of said second capacitor;

sixth switch means connected between said second power supply voltage and said second plate of said second capacitor;

seventh switch means connected between said second power supply voltage and said first plate of said second capacitor; and

,

eighth switch means connected between said second power supply lead and said second plate of said second capacitor;

wherein said fifth and said sixth switch means are closed, and said seventh and said eighth switch means are open during said second clock phase, thereby causing said second capacitor to be charged between said first power supply voltage and said second power supply voltage, and said seventh and said eighth switch means are closed and said fifth and said sixth switch means are open during said said first clock phase, thereby applying the negative of the voltage stored on said second capacitor during said second clock phase to said second power supply lead.

3. Structure as in claims 1 or 2 wherein said load devices are MOSFET devices having source leads serving as said first leads of said load devices, drain leads serving as said second leads of said load devices, and gate leads connected in common to said drain lead of said second load device.

4. Structure as in claims 1 or 2 wherein said inverting input transistor and said non-inverting input transistor are MOSFET devices.

5. Structure as in claim 3 wherein said inverting input transistor and said non-inverting input transistor are MOSFET devices.

6. Structure as in claims 1 or 2 wherein said switch means comprise MOSFET devices.

7. Structure as in claim 3 wherein said switch means comprise MOSFET devices.

8. Structure as in claim 4 wherein said switch means comprise MOSFET devices.

9. Structure as in claim 5 wherein said switch means comprise MOSFET devices.

10. The method of biasing a dynamic operational amplifier having a first lead connected to a first voltage supply and a second lead for connection to a biasing means, comprising:

connecting the first plate of a first storage capacitor to said first voltage supply and connecting said second plate of said first storage capacitor to a second voltage supply, thereby charging said first storage capacitor; and

connecting said first plate of said first storage capacitor to said second voltage supply and connecting said second plate of said first storage capacitor to said second lead;

whereby the voltage applied across said first lead and said second lead is equal to twice the voltage difference between said first and said second voltage supplies.

11. The method as in claim 10 wherein the first plate of a second storage capacitor is connected to said first voltage supply and said second plate of said second storage capacitor is connected to said second voltage supply, thereby charging said seconds storage capacitor, when said first storage capacitor is connected to said second lead;

and

said first plate of said second storage capacitor is connected to said second voltage supply and said second plate of said second storage capacitor is connected to said second lead when said first storage capacitor is connected to said first and second supply voltages;

whereby said second lead is always connected to either said first storage capacitor or said second storage capacitor.