Analog-to-digital and digital-to-analog converters and methods of operation

• US 4,431,987 A
• Filed: 02/25/1982
• Issued: 02/14/1984
• Est. Priority Date: 03/27/1980
• Status: Expired due to Fees

• Current Assignee: The Bendix Corporation (Honeywell International Inc.)
• Original Assignee: The Bendix Corporation (Honeywell International Inc.)
• Inventors: Whiteside, Arliss E.
• Primary Examiner(s): Sloyan, T. J.
• Application Number:
  US06/352,509
• Time in Patent Office: 719 Days
• Field of Search: 340/347 M, 340/347 DA, 340/347 AD, 340/347 CC
• US Class Current: 341/118
• CPC Class Codes: H03M 1/124 Sampling or signal conditioning arrangements specially adapted for A/D converters
• CPC Class Codes: H03M 1/40 recirculation type

Abstract

A method and apparatus for converting between analog signals and corresponding digital signals that is accurate relative to the actual value of the input signal, and not relative to the upper limit on the analog input signal. The method and apparatus are disclosed in terms of a serial-feed-back A/D converter that performs an A/D conversion through a plurality of cycles equal in number to the number of bits in the digital output word. In each cycle a comparison voltage is tested to determine if the bit output for the cycle is high or low. The comparison voltage is the amplified difference of the comparison voltage for the preceding cycle and another reference signal. The scale factor for the amplification of the difference between the two signals is one value if the bit value for the preceding cycle was high, and another complementary value if the bit value for the preceding cycle is low. The companion method and apparatus for converting a non-binary digital signal into a corresponding analog signal is also disclosed.

Claims

1. A method for converting a non-binary digital word to an analog signal comprising the steps of:

repetitively generating a predetermined set of timing signals in response to clock signals received from an external source;

decoding a received non-binary digital word to serially generate bit value signals having a first value when the received bit is high and a second value when the received bit is low;

generating an initial feedback signal V_p having a predetermined value in response to only the first timing signal in each set of timing signals;

generating a comparison signal V_c in response to said timing signals, a feedback signal V_p, a reference signal V_R, and said bit value signals, said comparison signal having a value

space="preserve" listing-type="equation">V.sub.c =(1-k)V.sub.p +kV.sub.r

when said bit value signal has said first value, and generating said comparison signal V_c having a value

space="preserve" listing-type="equation">V.sub.c =kV.sub.p

when said bit value signal has said second value, wherein k has a predetermined value in the range of 0<

k<

1/2, and V_R is a reference signal having a value equal to the full scale value of the analog signal;

storing said comparison signal V_c to generate said feedback signal V_p for use in the generation of the next sequential comparison signal V_c ;

repeating said steps of generating and storing said comparison signal in response to the remaining timing signals in said set of timing signals using the stored feedback signal V_p ; and

outputting said comparison signal V_c in response to the last timing signal in each set of timing signals to generate an analog output signal having a value corresponding to the value of the received non-binary digital word.

2. The method of claim 1 wherein the predetermined value of said initial feedback signal generated in response to said first timing signal is indicative of a common ground and has a value equal to zero.

3. The method of claim 1 wherein said step of generating a comparison signal V_c comprises the steps of:

transmitting said feedback signal V_p to the input of a unity gain amplifier through a first resistance R₁ having a predetermined value;

transmitting said reference signal V_R to the input of said unity gain amplifier through a second resistance R₂ in response to said bit value signal having said first value, said second resistance having a value related to the value of resistance R₁ according to the equation

space="preserve" listing-type="equation">R.sub.2 =((1-k)/k)R.sub.1

transmitting a ground potential to the input of said unity gain amplifier through a third resistance R₃ in response to said bit value signal having said second value, said third resistance R₃ having a value related to the value of said first resistance R₁ according to the equation

space="preserve" listing-type="equation">R.sub.3 =(k/(1-k))R.sub.1

and

amplifying the composite signal received at the input of said unity gain amplifier to generate said comparison signal V_c.

4. The method of claim 3 wherein said received digital word is a binary digital word, said method further preceded by the step of converting said binary digital word to a non-binary digital word.

5. The method of claim 3 wherein said step of generating a comparison signal requires a precise relationship between the values of resistances R₁, R₂, and R₃ and wherein the actual relationship between resistances R₁, R₂, and R₃ differ from said precise relationship causing the actual output signal to differ from the corresponding output analog signal, said method further preceded by the steps of:

determining from the actual relationship between resistances R₁, R₂, and R₃, a corrected non-binary word which will produce said corresponding output analog signal;

storing said corrected non-binary words in predetermined storage locations of an addressable storage array, the address of each corrected non-binary word being defined by the non-binary word corresponding to the output analog signal;

addressing said addressable storage array with the received non-binary digital word to output the corrected non-binary word for subsequent conversion to the corresponding output analog signal.

6. The method of claim 4 wherein the step of converting comprises the steps of:

storing a set of non-binary words in predetermined storage locations in an addressable storage array, the address of each non-binary word being defined by the corresponding digital word; and

addressing said addressable storage array with said binary word to output said non-binary word.

7. The method of claim 6 wherein said step of generating a comparison signal requires a precise relationship between the values of resistances R₁, R₂, and R₃ and wherein the actual relationship of resistances R₁, R₂ and R₃ differ from said precise relationship causing the actual output analog signal to differ from the desired analog signal, said step of converting said binary word further includes the steps of:

determining from the actual relationship between resistances R₁, R₂, and R₃, a corrected non-binary word which will produce said corresponding output analog signal; and

wherein said step of storing said non-binary words stores said corrected non-binary words in predetermined storage locations, the addresses of which are determined by the corresponding binary words.

8. The method of claim 1 wherein said received digital word is a binary digital word having a binary format, said method further includes the step of converting said binary word to a corresponding non-binary word prior to converting the non-binary word to a corresponding analog signal.

9. The method of claim 8 wherein said step of converting comprises the steps of:

storing a set of non-binary words in predetermined storage locations in an addressable storage array, the address of the predetermined storage locations being defined by the corresponding binary word;

addressing said addressable storage array with the received binary word to output the corresponding non-binary word.

10. The method of claim 9 wherein said step of generating a comparison signal requires a precise relationship between predetermined elements to produce the corresponding analog signal and wherein the actual relationship between the predetermined elements differ from the precise relationship causing an error in the output analog signal, said method further includes the steps of:

determining from the actual relationship between said predetermined elements the non-binary word corresponding to the analog signal represented by each binary word; and

wherein said step of storing a set of non-binary words stores the determined non-binary words in the storage locations defined by the corresponding binary word.

11. The method of claim 1 wherein said step of generating a comparison signal requires a precise relationship between predetermined elements and wherein the actual relationship between said predetermined elements differs from said precise relationship causing the actual output analog signal to differ from the desired output analog signal, said method further includes the steps of:

determining from the actual relationship between said predetermined elements a corrected non-binary word which will produce said corresponding output analog signal;

storing said corrected non-binary words in predetermined storage locations in an addressable storage array, the address of said corrected binary words being determined by the corresponding non-binary word; and

addressing said addressable storage array with said corresponding non-binary word to output said corrected non-binary word for subsequent conversion into an analog signal.

12. A non-binary digital to analog signal converter comprising:

timing signal generator means for repetitively generating a set of timing signals in response to clock signals received from an external clock;

decoder means for serially generating bit value signals in response to each bit of a received non-binary word, said bit value signal having a first value when the received bit is high and a second value when the received bit is low;

means for generating an initial feedback signal V_p having a predetermined value in response to the first timing signal of each set of timing signals;

means for generating a comparison signal V_c in response to said timing signals, said feedback signal V_p, a reference signal V_R, and said bit value signals, said comparison signal V_c having a first value

space="preserve" listing-type="equation">V.sub.c =(1-k)V.sub.p +kV.sub.R

when said bit value signal has said first value and a second value

space="preserve" listing-type="equation">V.sub.c =kV.sub.p

when said bit value signal has said second value;

wherein k has a predetermined value in the range from o<

k<

1/2, and V_R is said reference signal having a value equal to the full scale value of the analog signal;

means for temporarily storing the value of said comparison signal V_c to generate a feedback signal V_p in response to said timing signals, said means for temporarily storing further responsive to the next sequential timing signal for outputing said stored feedback signal V_p to said means for generating a comparison signal V_c ; and

means for outputting the last generated comparison signal V_c in response to the last timing signal in each set of timing signals;

where the value of said last comparison signal generated during each set of timing signals is said analog signal.

13. The converter of claim 12 wherein the predetermined value of the feedback signal generated by said initial feedback signal generator means is indicative of a common ground.

18. The converter of claim 12 wherein the received digital word is a binary digital word, and said converter further includes means preceding said non-binary digital to analog converter for converting said binary digital word to a corresponding non-binary digital word.

19. The converter of claim 18 wherein said means for converting is an addressable storage array storing a corresponding set of non-binary digital words in predetermined storage locations, the address of each stored non-binary word being defined in terms of its corresponding binary word.

20. The converter of claim 19 wherein said addressable storage array is a read only memory.

21. The converter of claim 19 wherein said feedback signal generator includes elements which must have a precise relationship to each other in order to generate the desired analog signal, and where any errors in said precise relationship between said elements will cause the generated analog signal to differ from the desired analog signal, and said addressable storage array stores non-binary digital words corresponding to the desired analog signals in the address locations defined by the received binary words.

22. The converter of claim 21 wherein the received digital word is a binary word, said non-binary to digital converter further includes an addressable storage array storing a corresponding set of non-binary digital words in predetermined storage locations, the address of each non-binary digital word being defined in terms of its corresponding binary digital word.

23. The converter of claim 22 wherein the ohmic value of resistances R₁ and R₂ differ from the desired relationship to resistance R₁ causing the generated analog signal to differ from the desired analog signal, said addressable storage array stores the non-binary word corresponding to the desired analog signal in the address locations defined by the received bindary digital word.

24. The converter of claims 23 or 22 wherein said addressable array is a read only memory.

14. The converter of claim 14 wherein said means for generating said comparison signal V_c comprises:

a unitary gain amplifier having an input and an output connected to said means for temporarily storing said comparison signal V_c and said means for outputting;

a first resistance R₁ having a predetermined value connected between said means for generating a first feedback signal V_p and the input of said operational amplifier;

means for generating said reference signal V_R in response to said bit value having said first value;

a second resistance R₂ connecting said means for generating said reference signal V_R to the input of said unity gain amplifier, said second resistance R₂ having an ohmic value related to the ohmic value of said first resistance R₁ according to the equation

space="preserve" listing-type="equation">R.sub.2 =((1-k)/k)R.sub.1

means for generating a ground signal in response to said bit value signals having said second value;

a third resistance R₃ connected between said means for generating a ground signal and the input of said unity gain amplifier, said third resistance R₃ having an ohmic value related to the value of said first resistance R₁ by the equation

space="preserve" listing-type="equation">R.sub.3 =(k/(1-k))R.sub.1

15. The converter of claim 14 wherein the received digital word is a binary digital word, said converter further includes means preceding said non-binary digital to analog converter for converting said binary digital word to a corresponding non-binary digital word.

16. The converter of claim 15 wherein said means for converting is an addressable storage array storing a corresponding set of non-binary digital words in predetermined storage locations, the address of each stored non-binary word being defined in terms of its corresponding binary digital word.

17. The converter of claim 16 wherein the ohmic values of resistances R₂ and R₃ differ from the desired relationship with respect to resistance R₁ causing the generated analog signal to differ from a desired analog signal, said converter further includes an addressable storage array preceding the non-binary to analog converter for storing non-binary words corresponding to the desired analog signals in address locations defined by received non-binary word.