Delay timer for a camera

• US 4,432,624 A
• Filed: 02/16/1982
• Issued: 02/21/1984
• Est. Priority Date: 02/16/1982
• Status: Expired due to Fees

• Current Assignee: Queen's University At Kingston
• Original Assignee: Queen's University At Kingston
• Inventors: Pipkorn, Mark G., Stevenson, Joan M.
• Primary Examiner(s): Gellner, Michael L.
• Application Number:
  US06/349,019
• Time in Patent Office: 735 Days
• Field of Search: 354/131, 354/238, 354/266, 354/267, 361/196
• US Class Current: 396/264
• CPC Class Codes: G03B 17/38 Releasing-devices separate from shutter integral with shutter G03B9/08

Abstract

A relatively inexpensive electronic delay timer particularly suitable for portable use in such applications as control of a camera shutter. The timer can be used in either a leading or trailing mode and employs a small 6V battery as a power source. An integrated circuit timer device is arranged to provide an output signal at the end of a time delay period which can be variably selected by means of a built-in capacitive-resistive network and which is arranged to start in response to a movement of an external control switch. The output signal triggers a second time period of predetermined duration in a second integrated circuit timer during which time a second output signal is generated thereform which is used to activate a transistor device, allowing a capacitor in the circuit to discharge therethrough and through a solenoid which is mechanically coupled to the camera shutter. When the second output signal ceases, at the end of the second time period, the transistor is deactivated and the capacitor recharges. The device is particularly adapted for use in sport coaching, professional and amateur photography and amateur naturalist pursuits.

Claims

1. A delay timer circuit comprising:

an externally controlled switch means;

first integrated circuit timer means arranged to provide a first output signal at the end of a selected first delay period initiated by said externally controlled switch means;

variable resistor-capacitor means for selecting duration of said first delay period;

circuit means for connecting said first integrated circuit timer means, through said externally controlled switch means, to a DC power source;

second integrated circuit timer means arranged to provide a second output signal for a predetermined time period initiated by said first output signal;

transistor means activated by said second output signal;

solenoid means arranged to mechanically activate an external load when a current is passed therethrough; and

capacitor means arranged to discharge a current through said solenoid means and said transistor means when said transistor means is activated, and to charge when said transistor means is deactivated.

2. A delay timer circuit as claimed in claim 1 including mode selecting means operatively connected to said externally controlled switch means.

3. A delay timer circuit as claimed in claim 2 wherein said first delay period is initiated when said externally controlled switch means is opened following a closure thereof.

4. A delay timer circuit as claimed in claim 2 wherein said first delay period is initiated when said externally controlled switch means is initially closed.

5. A camera-electronic delay timer combination comprising:

a camera having shutter means;

switch means for triggering said shutter means, remote from said camera;

first integrated circuit timer means arranged to provide a first output signal at the end of a selected first delay period initiated by operation of said switch means;

variable resistor-capacitor means for selecting duration of said first delay period;

circuit means for connecting said first integrated circuit timer means, through said switch means, to a DC power source;

second integrated circuit timer means arranged to provide a second output signal for a predetermined time period initiated by said first output signal;

transistor means activated by said second output signal;

solenoid means arranged to mechanically trigger said shutter means when a current is passed therethrough; and

capacitor means arranged to discharge a current through said solenoid means and said transistor means when said transistor means is activated and to charge when said transistor means is deactivated.

6. The combination of claim 5 including mode selecting means operatively connected to said switch means.

7. The combination of claim 6 wherein said first delay period is initiated when said switch means is opened following a closure thereof.

8. The combination of claim 6 wherein said first delay period is initiated when said switch means is initially closed.

9. The combination of claim 5 wherein said remote switch means is contained in a floor mat.