Limiter with dynamic hysteresis

• US 4,433,256 A
• Filed: 07/06/1982
• Issued: 02/21/1984
• Est. Priority Date: 07/06/1982
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Dolikian, Arman V.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/395,208
• Time in Patent Office: 595 Days
• Field of Search: 307/354, 307/358, 307/355, 307/359, 307/350, 307/540, 307/555, 328/147, 328/151, 328/169, 328/171, 328/172, 328/173, 328/175, 340/146.3 AC, 340/146.3 AE, 340/146.3 AG
• US Class Current: 327/73
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03K 5/084 modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal
• CPC Class Codes: H03K 5/153 Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant switching at zero crossing H03K17/13

Abstract

The invention is a limiter circuit with dynamic hysteresis for providing improved distortion immunity at the circuit output in response to an input signal. The limiter circuit includes a positive and negative peak detector. Two weighted averages are taken of the positive and negative peaks, preferably by means of a voltage divider network. The first input to a comparator circuit receives the input signal to the limiter circuit. Different voltages from the voltage divider network are applied to the second input of the comparator circuit so as to create a dynamic hysteresis effect in the comparator circuit. The different voltages are chosen in response to the output voltage from the comparator circuit by means of an analog switch. The comparator circuit includes a fixed hysteresis voltage for stabilizing the limiter circuit at low level voltage input signals.

Claims

1. A method for creating a limiter circuit with dynamic hysteresis comprising the steps of:

(1) detecting the positive and negative peaks of an input waveform,

(2) taking at least two weighted averages of said positive and negative peaks,

(3) alternately choosing one of said weighted averages,

(4) comparing said input waveform with said chosen weighted average,

(5) generating a first output signal if the chosen weighted average is greater than the input waveform and generating a second output signal if the chosen weighted average is less than the input waveform.

2. A method for creating a limiter circuit with dynamic hysteresis according to claim 1 with the additional step of:

(1) choosing one of said weighted averages in response to the generated output signals.

3. A limiter circuit with dynamic hysteresis for providing improved distortion immunity at the circuit output in response to a input signal, the limiter comprising,

detecting means for detecting the positive and negative peaks of said input signal,

means for taking a plurality of weighted averages of said positive and negative peaks,

comparator means having a first input responsive to said input signal,

means for alternately choosing at least one of said plurality of weighted averages and applying said at least one weighted average to a second input of said comparator means to create a dynamic hysteresis effect.

4. A limiter circuit according to claim 3 wherein said means for alternately choosing at least one of said plurality of weighted averages is responsive to the output from said comparator means.

5. A limiter circuit according to claim 3 or 4 wherein said means for alternately choosing at least one of said plurality of weighted averages is an analog switch.

6. A limiter circuit according to claim 3 wherein said means for taking a plurality of weighted averages is a voltage divider network.

7. A limiter circuit according to claim 3 wherein said comparator means includes a fixed hysteresis voltage for stabilizing said limiter circuit output at low level voltage input signals.

8. A limiter circuit with dynamic hysteresis for providing improved distortion immunity at the circuit output in response to a input signal, the limiter comprising,

means responsive to said input signal with a plurality of outputs proportional to said input signal,

switch means for alternately choosing one of said plurality of outputs,

comparator means responsive to said input signal and said switch means,

feedback means responsive to said comparator means to control said switch means.