Chip topography for MOS packet network interface circuit

• US 4,433,378 A
• Filed: 09/28/1981
• Issued: 02/21/1984
• Est. Priority Date: 09/28/1981
• Status: Expired due to Term

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Western Digital Corporation
• Inventors: Leger, Geary L.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/306,508
• Time in Patent Office: 876 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/100
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An optimum chip topography for a MOS LSI packet network interface circuit, including electrical interface and input/output circuitry disposed around the periphery of said chip and forming approximately a quadrilateral framework surrounding the remainder of the circuitry; a read only memory (ROM) disposed in one corner of the interface framework; a microcontroller disposed adjacent to the ROM and along part of a first side of the interface framework; direct memory access (DMA) circuitry disposed adjacent to the microcontroller and in a second corner of the interface framework; transmitter circuitry disposed adjacent to the DMA and microcontroller circuitry and along part of a second side of the interface framework; receiver circuitry disposed adjacent to the transmitter circuitry and in a third corner of the interface framework; data access line circuitry comprising part of a third side of the interface framework, and situated adjacent to the receiver circuitry; timing/counting circuitry disposed adjacent to the receiver circuitry and the data access line circuitry and in the fourth corner of the interface framework; read/write control circuitry comprising part of the fourth side of the interface framework, and situated adjacent to a portion of the receiver circuitry; input/output register circuitry disposed within the interior of the chip and adjacent to the timing/counting circuitry, the read/write control circuitry, the microcontroller, and the ROM; and internal register circuitry disposed within the interior of the chip and adjacent to the input/output register circuitry, the ROM, and the microcontroller. The invention further provides a novel indirect data addressing method and a data buffer allocation method for optimizing the use of the memory and processing resources of a host processor.

Claims

1. A metal oxide semiconductor (MOS) chip for a micro packet network interface circuit (MPAC) implementing a preselected packet network switching protocol, for use in conjunction with an external central processing unit (CPU) having a system memory, and for communicating with external communications circuitry, said MPAC comprising:

(a) chip interface circuitry adapted to couple said MPAC to signal lines of external circuitry;

(b) read/write control circuitry coupled to said CPU through said chip interface circuitry, for receiving control signals from and control sending signals to said CPU;

(c) timing/counting circuitry coupled to said read/write control circuitry, for indicating when a certain event has occurred and for counting the number of times said certain event has occurred;

(d) input/output (I/O) registers coupled to said read/write control circuitry, for storing control information received from said CPU through said read/write control circuitry;

(e) a microcontroller coupled to said I/O registers, for regulating the functions of the MPAC;

(f) read only memory (ROM) coupled to said microcontroller, for storing microinstructions used by said microcontroller;

(g) internal registers coupled to said microcontroller, for temporarily storing information for said microcontroller;

(h) a data control bus coupled to and controlled by said microcontroller, for routing control signals and data signals among certain circuitry of said MPAC;

(i) data access lines coupled to said CPU and said system memory through said chip interface circuitry, and to said I/O registers and said data control bus, for receiving information and transmitting information between said CPU and/or said system memory, and said data control bus and/or said I/O registers;

(j) direct memory access (DMA) circuitry coupled to said data control bus, and to said system memory through said chip interface circuitry, for accessing information from said system memory through said data control bus independently of said CPU;

(k) receiver circuitry coupled to said data control bus and to a serial input from said external communications communications circuitry through said chip interface circuitry, for receiving serial data from said external circuitry, for converting said serial data into a parallel format and verifying the validity of said data, and for making said data available to said data control bus;

(l) transmitter circuitry coupled to said data control bus and to a serial output to said external communications circuitry through said chip interface circuitry, for accepting data in parallel format from said data control bus and appending to said data certain control and verification information, and for converting said data to a serial format and transmitting said serial data to said external communications circuitry;

wherein said interface circuitry forms a quadrilateral outer framework on said MOS chip;

said ROM is disposed within one corner of said interface circuitry;

said microcontroller is disposed adjacent to said ROM and along part of a first side of said interface circuitry;

said DMA circuitry is disposed adjacent to said microcontroller, and within a second corner of said interface circuitry and along part of a second side thereof;

said transmitter circuitry is disposed adjacent to said microcontroller and said DMA circuitry, and along part of a second side of said interface circuitry;

said receiver circuitry is disposed adjacent to said transmitter circuitry, and within a third corner of said interface circuitry and along part of a third side thereof;

said data access lines comprise part of said third side of said interface circuitry, and are disposed adjacent to said receiver circuitry;

said timing/counting circuitry is disposed adjacent to said receiver circuitry and said data access lines and within the fourth corner of said interface circuitry;

said read/write control circuitry comprises part of the fourth side of said interface circuitry, and is disposed adjacent to said receiver circuitry;

said I/O registers are disposed adjacent to said timing/counting circuitry, said ROM, said microcontroller, and said read/write control circuitry; and

said internal registers are disposed adjacent to said I/O registers, said ROM, and said microcontroller.

2. The MOS MPAC chip as recited in claim 1, wherein said chip is housed in a dual-in-line semiconductor package wherein the voltage supply pins V_CC, V_DD, and V_SS are not symmetrically arranged around the perimeter of said semiconductor package in order to prevent damage to said MOS MPAC circuit if said semiconductor package is improperly inserted into a printed circuit board.

3. The MOS MPAC chip as recited in claim 1 wherein the circuitry of said chip is N-channel self-alligned silicon gate circuitry.

4. A metal oxide semiconductor (MOS) chip for a micro packet network interface circuit (MPAC) implementing a preselected packet network switching protocol, comprising chip interface circuitry, read/write control circuitry, timing/counting circuitry, input/output (I/O) registers, a microcontroller, read only memory (ROM), internal registers, a data control bus, data access lines, direct memory access (DMA) circuitry, receiver circuitry, and transmitter circuitry, all on a surface of said MOS chip,

(a) said read/write control circuitry coupled to said chip interface circuitry, said timing/counting circuitry, and said I/O registers;

(b) said microcontroller coupled to said I/O registers, said ROM, said internal registers, and said data control bus;

(c) said data access lines coupled to said chip interface circuitry, said I/O registers, and said data control bus;

(d) said DMA circuitry coupled to said data control bus and said chip interface circuitry;

(e) said receiver circuitry coupled to said data control bus and said chip interface circuitry; and

(f) said transmitter circuitry coupled to said data control bus and to said chip interface circuitry;

wherein said interface circuitry forms a quadrilateral outer framework on said MOS chip;

said ROM is disposed within one corner of said interface circuitry;

said microcontroller is disposed adjacent to said ROM and along part of a first side of said interface circuitry;

said DMA circuitry is disposed adjacent to said microcontroller, and within a second corner of said interface circuitry and along part of a second side thereof;

said transmitter circuitry is disposed adjacent to said microcontroller and said DMA circuitry, and along part of a second side of said interface circuitry;

said receiver circuitry is disposed adjacent to said transmitter circuitry, and within a third corner of said interface circuitry and along part of a third side thereof;

said data access lines comprise part of said third side of said interface circuitry, and are disposed adjacent to said receiver circuitry;

said timing/counting circuitry is disposed adjacent to said receiver circuitry and said data access lines and within the fourth corner of said interface circuitry;

said read/write control circuitry comprises part of the fourth side of said interface circuitry, and is disposed adjacent to said receiver circuitry;

said I/O registers are disposed adjacent to said timing/counting circuitry, said ROM, said microcontroller, and said read/write control circuitry; and

said internal registers are disposed adjacent to said I/O registers, said ROM, and said microcontroller.