Microcomputer system with input/output unit connected to the remainder of the system by a single multibit bus and several sequential data lines

• US 4,433,379 A
• Filed: 09/29/1980
• Issued: 02/21/1984
• Est. Priority Date: 10/31/1979
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Schenk, Manfred, Jeenicke, Edmund, Klotzner, Winfried
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/191,376
• Time in Patent Office: 1,240 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/4
• CPC Class Codes: F02D 41/24 characterised by the use of digital means
• CPC Class Codes: F02P 5/1514 with means for optimising the use of registers or of memories, e.g. interpolation
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: Y02T 10/40 Engine management systems

Abstract

The destination of commands provided by a microcomputer to an input-output unit over a data bus is provided without an address bus, while a control circuit in the input-output unit is connected with the microcomputer by connections for only three binary signals in one direction, "clear", chip-select and data strobe and one in the other, namely interrupt. The control circuit has a decoder connected to the data bus that sorts out the commands, feeding the outputs through a gate array that are enabled by the chip-select and data strobe signals for timing. Commands for switching, such as beginning and ending counts, and so on are one-byte commands directly transmitted to the appropriate circuits of the input-output. Read and write commands are two-byte commands sequenced by a sequencing and lockout circuit, the circuit selected in first byte being activated to read or write to or from the data bus in the second byte while the decoder is blocked. The direction of transmission of the data bus is controlled over a single connection from the control circuit in accordance with whether a write command is or is not present.

Claims

1. A simplified computer system having a computer unit of the so-called microcomputer type and an input-output unit, connected to said computer unit over a data bus, for transferring externally determined values to said computer unit, said input-output unit having a register-and-counter portion comprising a plurality of registers and a plurality of counters, said system further comprising the improvement which consists in that, in order to avoid the use of a separate multiple-connection address bus between said computer unit and said input-output unit:

only a single multibit bus serving as said data bus, and not substantially more than four one-way signal connections, of which two are respectively for chip-select (CS) and data strobe (DS) functions, are provided to interconnect said computer unit and said input-output unit, and for contribution to the addressing of said register-and-counter portion of said input-output unit, the latter unit has a control circuit (13) connected to a port of said data bus and also connected to said computer unit by said not more than four signal connections;

said control circuit (13) includes a decoder (40) having an input connected to said data bus port, for providing a variety of control commands and directing said commands from said data bus respectively to various registers and counters of said register-and-counter -portion by way of different outputs (41-46) of said decoder which are connected to said register-and-counter portion (76) of said input-output unit.

2. A computer as defined in claim 1 in which said variety of control commands are of just three kinds:

single-byte switching commands, plural-byte read commands and plural-byte write commands.

3. A computer system as defined in claim 1, in which said computer unit has a timing portion for supplying periodic data strobe signals having its output connected to said control circuit (13) of said input-output unit by said data strobe function connection (DS), a gate circuit array (47-52) being provided in said input-output unit at the output of said decoder (40) for permitting a control command to be given out only following reception of a data strobe signal from said computer unit coincident with the presence of a signal received from said computer over said chip-select function connection.

4. A computer system as defined in claim 3 in which said computer unit has means for producing chip-select signals and furnishing them to said input-output unit through said chip-select function connection (CS) of said computer, said gate circuit array (47-52) having groups of command connections (26,27,28) to said various registers and counters of said input-output unit and being connected for additional control by signals received over said chip-select connection (CS) from said computer unit for output selection among said groups of command connections (26,27,28).

5. A computer system as defined in claim 3 in which buffer storage means (57-57) are provided for supplying plural-byte commands, said buffer storage means having their inputts connected to those outputs of said gate circuit array which serve to transmit plural-byte commands from said decoder.

6. A computer system as defined in claim 4 in which buffer storage means (54-57) are provided for supplying plural byte commands, said buffer storage means having their inputs connected to those outputs of said gate circuit array which serve to transmit plural-byte commands from said decoder.

7. A computer system as defined in claim 5 or claim 6 in which said variety of control commands are of just three kinds, namely single-byte switching commands, plural-byte read commands and plural-byte write commands, and in which two of said not more than four connections between said computer unit and said control unit (13) of said input-output unit are respectively a clear function connection (CL) and an "interrupt" function connection (INT), sequencing circuits (74) being provided in said control circuit (13) for sequencing plural-byte commands and providing lockout protection therefor, said sequencing circuits having an input for "clear" commands connected to said clear function connection (CL) of said computer unit and having a program interrupt output connected to said interrupt function connection (INT) of said computer unit.

8. A computer system as defined in claim 7 in which said sequencing circuits (74) are so connected as to cause the first byte of a decoded plural-byte command to be stored in said buffer storage means, and in which, further, a second gate circuit array (59-62) is provided for transferring the contents of said buffer storage means to a corresponding output under control of said sequencing circuits (74).

9. A computer system as defined in claim 8 in which a second gate circuit array (59-62) is provided for transferring the contents of said buffer storage means to a corresponding output under control of said sequencing circuits (74) said sequencing circuits further containing a clearing circuit responsive to a "clear" command at their said input for clear commands, for clearing said buffer storage means after transfer of a plural-byte command.

10. A computer system as defined in claim 9 in which said sequencing circuits contain an additional gate circuit (65) for preventing the delivery of a program interrupt signal to said computer unit when a chip-select signal is present and/or when a decoded plural-byte command is being transferred by sad second gate circuit array (59-62).

11. A computer system as defined in claim 10 in which said sequencing circuits include logic circuit means (69,70) for distinguishing switching and read commands from write commands and in/response thereto reversing the direction of transmission of said data bus (11) according to whether or not a write command is present.