Enhancement mode JFET dynamic memory

• US 4,434,433 A
• Filed: 08/04/1980
• Issued: 02/28/1984
• Est. Priority Date: 02/21/1977
• Status: Expired due to Term

• Current Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
• Original Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
• Inventors: Nishizawa, Jun-ichi
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US06/174,724
• Time in Patent Office: 1,303 Days
• Field of Search: 357/22, 357/24, 357/23 R, 357/23 C, 357/23 VT, 357/23 TF, 357/13, 357/15, 357/41, 357/71, 357/55, 365/149, 365/150, 365/174, 365/177, 365/182, 365/185
• US Class Current: 257/264
• CPC Class Codes: G11C 11/35 with charge storage in a depletion layer, e.g. charge coupled devices
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 13/047 using electro-optical elements G11C13/042 takes precedence
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components

Abstract

A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in the current path to accomplish storing. Since the bulk mobility of a semiconductor is far larger than the surface mobility, the transit time of the carriers is much improved. Furthermore, since each structure of the memory cells is formed perpendicular to the semiconductor surface, the surface occupation area per memory cell is reduced. Thus, a high-speed and high-density semiconductor memory device is provided.

Claims

1. A semiconductor memory cell device formed in a semiconductor body and including at least one memory cell which comprises:

a first semiconductor region of a first conductivity type having a low resistivity;

a second semiconductor region of a second conductivity type opposite to said first conductivity type surrounding at least a portion of said first semiconductor region;

a third semiconductor region of said first conductivity type having a high resistivity and disposed on said first semiconductor region,

a fourth semiconductor region of said first conductivity type having a low resistivity and disposed on said third semiconductor region,

gate means disposed adjacent to said third semiconductor region between said first and fourth semiconductor regions for controlling the potential distribution in said third semiconductor region;

an insulating layer formed on said fourth semiconductor region;

a conductive electrode formed on said insulating layer,

said fourth semiconductor region, said insulating layer and said conductive electrode forming a capacitor;

means for conducting being electrically connected to said first semiconductor region,

said third semiconductor region having such impurity doping characteristics and dimensions that enable said potential distribution to form a potential barrier for charge carriers transporting between said first and fourth semiconductor regions by the influence of said gate means and that render the height of said potential barrier which approaches pinch-off to be controllable also by the voltage between said first and fourth semiconductor regions,

said semiconductor body having at least one recessed portion adjacent to said third semiconductor region, and said gate means is at least partially formed in said recess,

said memory cell device further comprising;

an insulating region filling said recess,

said conducting means including a fifth semiconductor region of said first conductivity type and of a low resistivity, and a metallic region embedded in said insulating region in said recess at least partially contacting said fifth semiconductor region;

one of said first region and said fourth region being provided in a surface of said semiconductor body, and the other being provided within said semiconductor body in a substantially vertical position relative to said surface of the semiconductor body.

2. A semiconductor memory device formed in a semiconductor body and including at least one memory cell which comprises:

a source region including a low resistivity semiconductor region of a first conductivity type for supplying retrieving charge carriers;

a storage region formed with a semiconductor region and disposed separate from said source region and constituting one electrode of a capacitor for storing signal charge;

means for forming the other electrode of said capacitor;

a channel region formed with a high resistivity semiconductor region of a second conductivity type opposite to said first conductivity type, disposed between said source region and said storage region and capable of forming a current path for charge carriers therebetween and establishing a potential barrier for charge carriers; and

said high resistivity channel region having such impurity doping characteristics and dimensions that render said high resistivity semiconductor region located between said source and said storage regions to be substantially depleted to provide a potential barrier for charge carriers without any bias applied to the memory cell and that render the height of said potential barrier to be controllable by at least the voltage applied between said source region and said other electrode means,

said at least one memory cell further comprising a gate means disposed in the neighborhood of said channel region for controlling the potential distribution in said channel region,

said gate means including a metal electrode which forms a Schottky electrode on said channel region.