Hierarchical computer system for generating selective output signals in response to received input signals

• US 4,434,460 A
• Filed: 06/18/1980
• Issued: 02/28/1984
• Est. Priority Date: 06/18/1979
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wallmark, Erik I., Enser, Mats A., Grebner, Kurt G. E., Drakenborn, Karl-Gunnar
• Primary Examiner(s): Nusbaum, Mark E.
• Assistant Examiner(s): Fleming, Michael R.
• Application Number:
  US06/160,760
• Time in Patent Office: 1,350 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/178, 364/179, 340/825.31, 235/382, 235/92 DP, 318/636
• US Class Current: 710/65
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G07C 1/10 together with the recording, indicating or registering of other data, e.g. of signs of identity

Abstract

Hierarchical three-level computer system for receiving input messages from signal sources (23) and for conditionally activating output devices (26) according to input messages; the system comprising a host computer (15), a terminal computer (27) and a number of micro computers (22). The central computer enters condition tables into specific storage modules (2A-2E) within the terminal computer. These tables can be displayed on the terminal computer screen (10) and may be updated from the terminal computer keyboard (8). The micro computer receives input signals from a signal source (22) and composes input messages, which are transferred to the terminal computer. The terminal computer makes a comparison between input messages and condition table data and selectively activates the output devices (26).

A specific up and down counting apparatus within the micro computer enables a simultaneous signal detection and data processing operation.

Claims

1. A computer system wherein a microcomputer comprising an arithmetic unit and a plurality of registers is connected to a signal source and a computer, said microcomputer is programmed for decoding an input signal from said signal source composing the decoded signal into an message, and transmitting the message to said computer, the improvement comprising:

said microcomputer comprising means for detecting the change in level of the input signal;

said microcomputer comprising means for decrementing which is operatively connected to a first of said registers and responsive to said detecting means, wherein said decrementing means decrements the contents of said first register from a first predetermined value commencing +1 clock cycles after the input signal changes level, whereby n clock cycles are available to the microcomputer to compose said message;

said microcomputer unit further comprising a means for loading said first register with a second predetermined value from a second of said registers when said first register means reaches zero, a means responsive to the detection means for incrementing said first register, said second predetermined value is incremented until the input signal again changes level, and means responsive to the detection means to generate a new first predetermined value and a new second predetermined value from the final incremented value in said first register.

2. The computer system of claim 1 wherein said second predetermined value is generated by said generating means to be substantially three-fourths of the count in said first register at the time when said input signal level changes;

and wherein said first predetermined value is generated by said generating means to be equal to said second predetermined value minus a constant value K.

3. The computer system according to claim 2 wherein said constant value K is the value by which the first register would be decremented in said n clock cycles whereby said n clock cycles are made available for composing said message from said signal information before said decrementing means commences decrementing said first register.

4. The computer system of claim 3 wherein said computer is a terminal unit which is connected to each of a plurality of micro computers and includes storage tables having information to be compared by a program in said terminal unit with said signal information in said message from a micro computer, each of said tables being displayable to an operator of said terminal unit;

a plurality of output devices connected to said terminal unit, an output being responsive to a favorable comparison of said signal information from a related signal source, with an item of information in said storage tables.

5. The computer system of claim 4 wherein said storage tables further comprise:

a first displayable storage module storing a table defining the class of each signal source;

a second displayable storage module storing a class index table defining the class of an incoming message;

a third displayable memory module storing a validity table defining the validity of an incoming message;

a fourth displayable storage module storing a host error message table for receiving error messages to be transferred to the central computer;

and a fifth displayable storage module storing a terminal error message table for receiving messages to be processed in the terminal.

6. The computer system of claim 2 wherein said signal source comprises a magnetic card reader and said output device comprises a door lock.

7. The computer system of claim 6 wherein the storage modules store tables for comparison with employee number input signals.