Branch predicting computer

• US 4,435,756 A
• Filed: 12/03/1981
• Issued: 03/06/1984
• Est. Priority Date: 12/03/1981
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Potash, Hanan
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/326,837
• Time in Patent Office: 824 Days
• Field of Search: 364/200
• US Class Current: 712/237
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G06F 9/3846 using static prediction, e.g. branch taken strategy

Abstract

Disclosed is a digital computer which includes means for storing a plurality of instructions arranged as a program with conditional branch instructions at respective locations in said program specifying conditions to be tested; an instruction prefetch means and an instruction execute means for respectively fetching and executing different instructions of said program at the same time in a pipelined fashion; said conditional branch instruction at each of said locations further having multiple encodings which predict the state of the condition to be tested; and a control means for detecting when said prefetch means has fetched one of said conditional branch instructions and for fetching the next instruction based on the predicted state of the condition to be tested and encoded in said fetched conditional branch instruction.

Claims

1. An improved digital device including a memory means for storing a plurality of instructions arranged as a program with conditional branch instructions at respective locations in said program specifying conditions to be tested;

an instruction prefetch means and an instruction execute means for respectively fetching and executing different instructions of said program at the same time in a pipelined fashion;

said conditional branch instruction at each of said locations further having multiple encodings which predict the state of the condition to be tested; and

a control means for detecting when said prefetch means has fetched one of said conditional branch instructions and for fetching the next instruction based on the predicted state of the condition to be tested and encoded in said fetched conditional branch instruction.

2. A device according to claim 1 and further including a writing means for changing said encoding of said fetched conditional branch instruction at its memory location in a predetermined fashion in response to that instruction having an encoding which predicts a state of said condition that is different than the actual state of said condition at the time when that instruction is executed in said pipeline by said execute means.

3. A device according to claim 1 and further including means for detecting other encodings of said fetched conditional branch instruction which give a history of how said predicted state of said condition compared with the actual state of said condition during previous executions of the fetched conditional branch instruction.

4. A device according to claim 3 and further including a writing means for changing the encoding of said fetched conditional branch instruction in a predetermined fashion at its memory location in response to said means for detecting having detected that the predicted state of said condition was different than the actual state of said another condition the last time said fetched conditional branch instruction was executed by said execute means.

5. A device according to claim 1 wherein said conditional branch instruction has an operation code, and said multiple encodings are encodings of said operation code.

6. A device according to claim 5 wherein said encodings of said operation code of said conditional branch instruction are binary encodings.

7. A device according to claim 1 wherein said device is a digital computer.

8. A programmable digital device including a memory means for storing a plurality of instructions arranged as a program;

a conditional branch instruction at one location in said program having a first encoding specifying a condition to be tested and predicting a first state of said condition;

another conditional branch instruction at another location in said program having a second encoding specifying said same condition to be tested and predicting a second state of said condition; and

a means for fetching said conditional branch instruction from any one of said locations and for thereafter fetching the next instruction from said program based on said predicted state of said condition as encoded in said fetched conditional branch instruction.

9. A programmed digital device including a memory means for storing a plurality of instructions arranged as a program;

at least one of said instructions being a conditional branch instruction specifying a condition to be tested;

said at least one conditional branch instruction having at least a first encoding predicting a first state of said condition and having at least a second encoding predicting a second state of condition.