Raster memory manipulation apparatus

• US 4,435,792 A
• Filed: 06/30/1982
• Issued: 03/06/1984
• Est. Priority Date: 06/30/1982
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Bechtolsheim, Andreas
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/393,599
• Time in Patent Office: 615 Days
• Field of Search: 365/63, 365/174, 365/182, 365/189, 365/193, 365/230, 365/231, 365/233, 365/234, 365/235
• US Class Current: 365/189.02
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

An apparatus for manipulating and displaying raster images stored in a memory system under computer control, wherein a function unit combines new display data presented to the apparatus with display data already stored in memory, to form a new display that is stored in memory system, all in a single read/modify/write cycle.

Claims

1. A memory apparatus for use in computer controlled display systems, which is responsive to memory location data and display data supplied by the computer during a memory access cycle, comprising

memory means for storing the display data, wherein the stored display data are arranged in a plurality of groups of bit locations which form a bit map and in which each group of locations is designated by a row and column address and further wherein bit locations within each designated group are enabled for access by row and column address strobes applied during the memory access cycle;

and

addressing means coupled to the memory means and responsive to the memory location data for sequentially generating a plurality of row and column addresses and a plurality of row and column address strobes during each memory access cycle, which strobes are specified by the memory location data and correlated to the plurality of row and column addresses, so that specified bit locations in a plurality of groups of bit locations can be accessed during the memory access cycle to permit any desired portion of the bit map to be accessed during a single memory access cycle.

2. The apparatus of claim 1 wherein the computer issues a write request in order to initiate a memory access cycle, and furtherwherein the addressing means include

means for converting the memory location data into the plurality of row and column addresses and the plurality of row and column address strobes;

and

timing means, responsive to the write request, for controlling the sequence in which each of the plurality of row and column addresses and row and column address strobes are generated and applied to the memory means, so that the desired portion of the bit map can be modified in a single memory access cycle.

3. The apparatus of claim 2 wherein the computer issues a read request to initiate a memory access cycle, and furtherwherein, the addressing means include

means for converting the memory location data into the plurality of row and column addresses and the plurality of row and column address strobes;

and

timing means responsive to the write request for controlling the sequence in which each of the plurality of row and column addresses and row and column address strobes are generated and applied to the memory means, so that the desired portion of the bit map can be read in a single memory access cycle.

4. The apparatus of claim 2, wherein the memory means comprise a plurality of random access memories each of which provide one bit location for each row and column address and each of which receive the plurality of row and column addresses in parallel and the row address strobes in common, and further wherein the addressing means selectively apply the column address strobes to ones of the plurality of random access memories so that a bit of data can be stored in each random access memory which receives a column address strobe.

5. The apparatus of claim 4 wherein the converting means supply to designated ones of the random access memories column address strobes in a first set of address strobes which are correlated to a first set of rows and column addresses and supply to different designated ones of the random access memories column address strobes in a second set of column address strobes which are correlated to a second set of row and column addresses.

6. The apparatus of claim 5 wherein the first and second sets of column address strobes are supplied to the random access memories in conjunction with the first and second set of row and column addresses consecutively and within a single memory access cycle.

7. The apparatus of claim 6 wherein the memory location data includes the row and column address of the group of bit locations which contains the location at which the portion of the bit map to be modified begins, and an offset quantity which is the number of bits by which the starting location is offset from the group address, and furtherwherein the addressing means comprise

means for extracting the row and column address from the word address and for producing a first column address which is identical to the column address;

incrementing means responsive to the column address and to the timing means for incrementing the column address to the next consecutive column address to produce a second column address; and

decoder means, responsive to the offset quantity, for generating the first and second sets of column address strobes, so that upon application of the first set of column address strobes, only those random access memories which contain bit locations within the bit map portion to be modified are accessed, and so that upon application of the second set of column address strobes only those random access memories addressed by the second column address and having bit locations within the memory portion to be modified, are accessed.

8. The apparatus of claim 7 wherein the decoder means comprise a read only memory which is addressed by the offset quantity.

9. The apparatus of claim 7 wherein the incrementing means is a binary adder.

10. The apparatus of claim 7 wherein the memory address further includes width data which is indicative of the width of the bit map portion to be modified and further wherein the decoder means are further responsive to the width data so that the quantity of the column address strobes in the first and second sets of address strobes are varied so that the portions of the memory means which are modified are variable in width.

11. The apparatus of claim 1 in which the computer supplies function specification data, further including function generating means, responsive to the binary data and to the function specification data from the computer and to the bit map data in the memory means, for performing a specified Boolean operation upon the bit map data and the binary data, wherein the Boolean operation is specified by the function specification data.

12. The apparatus of claim 11 wherein the function generating means comprise multiplexer means having a plurality of data input lines and a plurality of control lines, wherein the binary data are applied to one of the plurality of control lines and the stored binary data are applied to another of the plurality of control lines, and furtherwherein each data line receives a different one of the bits of the function specification data, so that the output of the multiplexer means takes the form of the binary and bit map data which have been operated upon by a Boolean function which is specified by the function specification data.

13. The apparatus of claim 3, wherein the memory location data includes alignment data, further including shifter means responsive to the display data and to the alignment data for aligning the display data with the bit locations being addressed.

14. The apparatus of claim 1, further including an output device responsive to the bit map data for displaying the bit map data.

15. The apparatus of claim 14, wherein the output device is a raster scan display.

16. The apparatus of claim 14, wherein the output device is a laser printer.

17. A bit-wise modifiable memory apparatus for use in computer controlled display systems in which a computer supplies display data, memory location data and function control signals, for storing the display data and for modifying the stored data and in which a display device receives the stored data for display, the apparatus comprising

memory means for storing a plurality of binary words having a predetermined length, each word being stored at a location which is defined by a row and column address, wherein data are stored during a write cycle memory access and the stored data are read out during a read cycle memory access and further wherein row and column address strobes enable the memory to store data at specific bits within the word addressed;

multiplexer means, responsive to the display data, to the stored data, and to the function control signals, wherein the multiplexer has a plurality of data input lines and a plurality of control lines, and further wherein the function control signals are applied to the plurality of data lines, and the display data and the stored data are applied to the plurality of control lines, for providing modified data which result from a selected Boolean operation upon the display data and the stored data, the selected Boolean function being specified by the function control signals; and

addressing means, responsive to the memory location data, for providing the row address and a first and second column address which specify the location of the words being modified, and for providing the row address strobe and a first and second set of column address strobes for enabling the bits within the addressed words which are to be modified, wherein the first column address is generated simultaneously with the first set of column address strobes, and the second column address is generated simultaneously with the second set of column address strobes, all during a single memory access cycle, so that at least two words of data can be accessed and modified in the single memory access cycle.

18. A Boolean modifiable memory apparatus in which data stored within memory are modified in accordance with input data and function data, comprising

memory means for supplying stored data from a specified location during a memory read cycle and responsive to modified data for storing modified data at a specified location during a memory write cycle;

and

multiplexer means, responsive to the modified data supplied from the memory means, to the input data, and to the function data, for supplying the modified data to the memory means for storage,

wherein the multiplexer means have a plurality of data lines and a plurality of control lines and are operable to supply, as an output, data which are present on one of the plurality of data lines, in accordance with the combination of data present on the plurality of control lines, and

furtherwherein the function data are supplied to the data lines of the multiplexer means, the stored data are applied to ones of the plurality of control lines, and the input data are supplied to different ones of the plurality of control lines, so that the output of the multiplexer means corresponds to a Boolean function of the stored data and the input data, the Boolean function being specified by the function data;

whereby the stored data and the input data are supplied to the control lines and the function data are supplied to the data lines all during the memory read cycle, and the modified data, which is the result of the specified Boolean operation upon the stored data and input data, are supplied to the memory means for storage during the memory write cycle.

19. The apparatus of claim 18 in which the stored data are output by the memory means and the input data are each supplied in a parallel word format having a first predetermined number of bits, wherein the multiplexer means comprise a plurality of data selectors equal in number to the first predetermined number, each data selector having a second predetermined number of control lines and a third predetermined number of data lines, and further wherein one control line of each data selector receives one bit from the stored data word and another control line of each data selector receives one bit from the input data word, with each data selector receiving different bits of the input data word and the stored data word;

and wherein all data selectors receive the same function data on their data lines.

20. The apparatus of claim 19 wherein there are sixteen data selectors, each data selector having two control lines and four data lines, and further wherein the input data and the stored data are formatted in parallel sixteen-bit words.

21. The apparatus of claim 19 wherein the data selectors are multiplexers.