Semiconductor memory device with dummy word line/sense amplifier activation
First Claim
1. A semiconductor memory device comprising:
- a plurality of semiconductor memory cells;
at least one word line coupled to said plurality of semiconductor memory cells for selectively transmitting an access signal thereto;
at least one pair of data lines coupled to said plurality of semiconductor memory cells for transferring data with respect thereto;
sense amplifier means coupled to said at least one pair of data lines for amplifying a data signal transferred therethrough;
a dummy word line having a signal transfer property corresponding to that of said at least one word line;
a dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an addressing operation is effected; and
energizing signal generating means coupled to said dummy word line for generating a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier means in response to a dummy selection signal transmitted through said dummy word line.
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Accused Products
Abstract
A semiconductor memory device is provided, including a plurality of MOS memory cells arranged in a matrix fashion, word lines for selectively transferring an access signal to the MOS memory cells, plural pairs of data lines for effecting data transfer with resepct to the MOS memory cells, sense amplifiers connected to the plural pairs of data lines to amplify data signals on the data lines, and a clock pulse generator connected to produce a clock pulse for activating the sense amplifiers. The memory device further includes a dummy word line arranged in the same manner as the word lines, and a dummy decoder connected to energize the clock pulse generator through the dummy word line so that the clock pulse generator produces a clock pulse to activate the sense amplifiers for preset period of time.
406 Citations
27 Claims
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1. A semiconductor memory device comprising:
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a plurality of semiconductor memory cells; at least one word line coupled to said plurality of semiconductor memory cells for selectively transmitting an access signal thereto; at least one pair of data lines coupled to said plurality of semiconductor memory cells for transferring data with respect thereto; sense amplifier means coupled to said at least one pair of data lines for amplifying a data signal transferred therethrough; a dummy word line having a signal transfer property corresponding to that of said at least one word line; a dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an addressing operation is effected; and energizing signal generating means coupled to said dummy word line for generating a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier means in response to a dummy selection signal transmitted through said dummy word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor memory device comprising:
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a plurality of semiconductor memory cells arranged in a matrix array; a plurality of word lines each commonly coupled to the semiconductor memory cells on the same row; a plurality of pairs of data lines each pair commonly coupled to the semiconductor memory cells on the same column for the transfer of data with respect to these memory cells; sense amplifier means coupled to said plurality of pairs of data lines for amplifying data transferred through one of said data line pairs; a dummy word line having a signal transfer property corresponding to those of said word lines; dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an address designating operation is effected; and energizing signal generating means, coupled to said dummy word line for producing a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier means in response to a dummy selection signal transmitted through said dummy word line. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A semiconductor memory device comprising:
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a plurality of semiconductor memory cells arranged in a matrix array; a plurality of word lines each commonly coupled to the semiconductor memory cells in each row of said matrix array; a plurality of data lines each commonly coupled to the semiconductor memory cells in each column of said matrix array for the transfer of data with respect to these memory cells; a sense amplifier means coupled to said plurality of data lines for amplifying data transferred through one of said data lines; a dummy word line having a signal transfer property corresponding to those of said word lines; a dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an address designating operation is effected; and energizing signal generating means coupled to said dummy word line for producing a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier in response to a dummy selection signal transmitted through said dummy word line. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification