High terminal count integrated circuit device package

• US 4,437,141 A
• Filed: 09/14/1981
• Issued: 03/13/1984
• Est. Priority Date: 09/14/1981
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Prokop, Jon S.
• Primary Examiner(s): Kucia, R. R.
• Application Number:
  US06/301,698
• Time in Patent Office: 911 Days
• Field of Search: 361/406, 361/403, 361/395, 361/412, 174/68.5
• US Class Current: 361/771
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H05K 2201/049 PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/09181 Notches in edge pads
• CPC Class Codes: H05K 2201/10666 Plated through-hole for surface mounting on PCB
• CPC Class Codes: H05K 3/3442 having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: H05K 3/368 parallel to each other H05K3/361 takes precedence
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

An integrated circuit (IC) device package is disclosed suitable for accommodating large terminal count IC devices in a very small space. A first set of terminals is located in notches around the periphery of the package. A second set of terminals is located inboard of the package and are comprised of metallized annular rings on the top and bottom surfaces of the package around holes or apertures through the surfaces of the package with metallization coating the holes to connect the top and bottom annular rings. This second set of terminals may be arranged in rows parallel to the edges of the package and may be connected to the IC device through buried conductor traces and wire bonding techniques. If necessary, additional rows of metallized holes can be utilized in a grid configuration, preferably at 0.050" centers.

Claims

1. A surface mounted high terminal count integrated circuit device package for solder attachment to a substrate comprising:

(a) a support member having a centrally disposed chip connect area, top and bottom surfaces and periphery forming sides and walls forming notches in the sides of said support member and a plurality of holes in said support member in preselected patterns adjacent to the notched periphery thereof;

(b) electrical metallizations on the walls of said notches and plurality of holes of the support member, said metallization of the notches forming metallized notches and said metallization of the holes forming cylindrically shaped electrical leads therethrough, said metallized notches and holes for forming solderable connections between the package and substrate;

(c) a plurality of wire bonding terminals selectively positioned on the support member adjacent said chip connect area;

(d) a plurality of trace conductors having first and second ends, said first ends electrically connected to said plurality of wire bonding terminals; and

(e) a plurality of expanded terminal pads mounted on the top and bottom surfaces of the support member, said expanded pads of the top surface electrically connected to the second ends of the trace conductors and together with the expanded pads of the bottom surface electrically connected to the notch and hole metallizations of the support member in open communication with the metallized notches and holes thereof whereby when the bottom pads are soldered to the substrate, solder rises up the open metallized notches and holes to form solder fillets therein for electrical connection of the substrate and for visual inspection thereof.

2. A surface mounted integrated circuit device package according to claim 1 wherein the expanded pads for the metallized hole terminals are annular metallized pads.

3. A surface mounted integrated circuit device package according to claim 1 wherein said trace conductors are positioned at different levels within the support member to interconnect the integrated circuit terminals with the peripheral and metallized hole terminals.

4. A surface mounted high terminal count integrated circuit device package according to claim 1 wherein selected ones of said expanded pads on the bottom surface of said substrate are raised.

5. A surface mounted high terminal count integrated circuit device package according to claim 1 wherein said plurality of metallized hole terminals are located behind said peripheral terminals.

6. A surface mounted high terminal count integrated circuit device package according to claim 1 wherein selected ones of said plurality of metallized hole terminals form a first set of metallized hole terminals alternated between said peripheral terminals.

7. A surface mounted high terminal count integrated circuit device package according to claim 1 wherein said plurality of metallized hole terminals include a second set of metallized hole terminals in proximity to the first metallized hole terminals.

8. A surface mounted high terminal count integrated circuit device package according to claim 7 wherein the two sets of metallized hole terminals of the plurality of hole terminals form a grid pattern.

9. A surface mounted high terminal count integrated circuit device package according to claim 8 wherein said grid pattern is a square.

10. A surface mounted high terminal count integrated circuit device package according to claim 9 wherein the first and second metallized hole terminals of said plurality of hole terminals are on centers equal to or less than 0.100".

11. A surface mounted high terminal count integrated circuit device package according to claim 1 wherein said support material is an insulator.

12. A surface mounted high terminal count integrated circuit device package according to claim 11 wherein said insulator is a ceramic.