Process for producing NPN type lateral transistor with minimal substrate operation interference

• US 4,437,226 A
• Filed: 12/16/1982
• Issued: 03/20/1984
• Est. Priority Date: 03/02/1981
• Status: Expired due to Term

• Current Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Original Assignee: Rockwell International Corporation
• Inventors: Soclof, Sidney I.
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US06/450,309
• Time in Patent Office: 460 Days
• Field of Search: 29/576 W, 29/576 B, 29/578, 29/580, 29/577 R, 148/187, 156/643, 427/93
• US Class Current: 438/337
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 29/6625 Lateral transistors H01L29/66242 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/735 Lateral transistors
• CPC Class Codes: Y10S 148/051 Etching
• CPC Class Codes: Y10S 148/085 Isolated-integrated
• CPC Class Codes: Y10S 148/096 Lateral transistor
• CPC Class Codes: Y10S 148/143 Shadow masking

Abstract

The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping P+ which is driven in from one side only while N+ is introduced and driven in from both sides, thereby providing an N+, P+P, N+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Claims

1. A method for forming an array of sub-micron dimensioned NPN-type lateral transistors on a substrate doped P-type, wherein each transistor is formed comprising the following steps:

masking the substrate to outline a pair of boundary regions for each semi-array of active regions to comprise a transistor;

slotting the substrate in said boundary regions to a given depth to form spaced apart slots removing any masking material from the substrate;

angle evaporating etch resist to cover the active regions of the substrate between slots; and

the edges of said slots to a depth less than said given depth by way of the slots;

etching away the substrate below said depth less than the given depth sufficiently to separate the semi-arrays of active regions from the substrate except at spaced apart locations therealong;

oxidizing the substrate to fill in the portions etched away and the slots;

slotting the substrate orthogonally to the first mentioned slots to provide second slots with orthogonal pairs of slots defining active regions for the respective transistors;

doping the regions defined by orthogonal pairs of slots P+ through a single corresponding edge of each of the second slots and driving in the P+ doping;

doping of said last mentioned regions through both edges of each slot of said second slots N+ and driving in the N+ doping;

oxidizing the substrate to completely isolate said active regions from the substrate; and

,

establishing electrical connections to the outer N+ regions and inner P+P region.