Device for changing the electrical circuit configuration of integrated semiconductor circuits

• US 4,438,347 A
• Filed: 08/07/1981
• Issued: 03/20/1984
• Est. Priority Date: 08/13/1980
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Gehring, Gerhard
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US06/291,112
• Time in Patent Office: 956 Days
• Field of Search: 307/303, 307/304, 307/308, 357/84, 357/86, 357/74
• US Class Current: 327/511
• CPC Class Codes: H01C 17/23 by opening or closing resistor geometric tracks of predetermined resistive values, e.g. snapistors
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 2203/45696 the LC comprising more than two resistors
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 2203/45726 the LC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 3/45623 using switching means

Abstract

Device for changing the electrical circuit configuration of integrated semiconductor circuits on chips for the adjustment and trimming of circuit parameters, including circuit connections selectively disposed in the circuit configuration of the integrated semiconductor circuits, the circuit connections being accessible from outside the circuit chips and being mechanically openable without mechanically and without electrically stressing and modifying the circuit chips.

Claims

1. Device for changing the electrical circuit configuration of integrated semiconductor circuits on chips for the adjustment and trimming of circuit parameters, comprising circuit connections selectively disposed in the circuit configuration of the integrated semiconductor circuits, said circuit connections being accessible from outside the circuit chips and being mechanically openable without mechanically and without electrically stressing and modifying the circuit chips, an integrated semiconductor circuit having electrical interference signals caused by stored mechanical stresses, an evaluation circuit following said semiconductor circuit, and a balancing resistor network disposed in said evaluation circuit, said circuit connections being in the form of bridges connected to resistors of said resistor network and being mechanically openable for selectively adjusting resistance values of said resistor network and compensating said interference signals.

2. Device according to claim 1, wherein said semiconductor circuit is a magnetic field-controlled circuit having a Hall-effect generator as a magnetic-electrical sensor, and said evaluation circuit is an amplifier.

3. Device according to claim 1, wherein said evaluation circuit is an amplifier having a load circuit and said resistor network is disposed in said load circuit.

4. Device according to claim 1 or 3, including a micropack in which said integrated circuit is mounted, contact pads disposed in said micropack and conductor runs leading to said contact pads, said circuit connections being operable to disconnect said conductor runs for the selective adjustment of resistance values of said balancing resistor network.

5. Device according to claim 4, including a non-magnetic metal cap disposed in said micropack covering said integrated circuit.