Monolithic programmable gain-integrator stage

• US 4,438,354 A
• Filed: 08/14/1981
• Issued: 03/20/1984
• Est. Priority Date: 08/14/1981
• Status: Expired due to Term

• Current Assignee: ON Semiconductor Corporation
• Original Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Inventors: Haque, Yusuf A., Schuler, Jeffrey A., Saletore, Vikram
• Primary Examiner(s): Heyman, John S.
• Assistant Examiner(s): Callahan, Timothy P.
• Application Number:
  US06/292,870
• Time in Patent Office: 949 Days
• Field of Search: 328/127, 307/493, 307/491, 330/9, 330/284, 330/144
• US Class Current: 327/337
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence
• CPC Class Codes: H03G 3/001 Digital control of analog signals

Abstract

A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100, 101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (V_error) is inverted and integrated one time for each integration of the input voltage (V_in), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (V_out).

Claims

1. An electronic gain-integrator stage having an input terminal for receiving an input signal and having an output terminal, comprising:

M operational amplifier gain stages connected in series where M is a selected integer varying from 1 to K, where K is the maximum number of gain stages, said M operational amplifier gain stages each having a programmable gain and an inherent offset voltage and said Mth gain stage having an output lead which provides an output signal which includes an error component which is a function of said offset voltages of said M operational amplifier gain stages;

an operational amplifier integrator stage connected to said gain stages, having an inherent offset voltage, and including

means for integrating during the first half of a selected cycle the negative of said error component, which is produced in response to the initialization of said M gain stages, and integrating during the second half of said selected cycle both the positive of said error component, which is produced in response to said input signal, and the positive of said input signal multiplied by each of said programmable gains of each of said M gain stages;

wherein the negative of said error component is integrated once for each integration of the input signal, whereby the effects of said offset voltages of each of said M gain stages are eliminated.

2. The structure as in claim 1 wherein each said operational amplifier gain stage comprises:

an operational amplifier having an inverting input lead, a noninverting input lead connected to a reference voltage, and an output lead;

feedback means containing a passive element connected between said inverting input lead and said output lead of said operational amplifier;

an array of N passive components connected between said inverting input lead and an input terminal, where N is a selected integer varying from 1 to J, where J is the maximum number of passive components; and

a plurality of switch means for selectively connecting between said inverting input lead of said operational amplifier and said input terminal desired ones of said N passive elements of said array;

whereby said programmable gain of said operational amplifier gain stage is determined by the value of said selected ones of said N components of said array.

3. Structure as in claim 2 wherein said array of N passive components comprises N capacitors and said feedback means comprises a capacitor.

4. Structure as in claim 3 wherein said capacitors of said array are binary weighted, wherein the capacitance value of each capacitor is equal to 2^L-1 C, where L is a first integer ranging from 1 to N, and N is a second integer equal to the number of passive elements in the array.

5. Structure as in claim 2 wherein said programmable gain of each of said operational amplifier gain stage is selected once for each integration of the input signal.

6. The structure as in claim 1 wherein said means for integrating further comprises means for applying to said operational amplifier integrator stage a voltage equal to the voltage to be integrated minus said inherent offset voltage of said operational amplifier integrator stage, such that said operational amplifier integrator stage integrates said voltage to be integrated and produces an output signal free from the effects of said inherent offset voltage of said operational amplifier integrator stage.

7. The structure as in claim 6 wherein said operational amplifier integrator stage comprises:

an operational amplifier having an inverting input lead serving as the input lead of said operational amplifier integrator stage, a noninverting input lead connected to a reference voltage, and an output lead;

a first buffer amplifier having an input lead connected to said output lead of said operational amplifier of said operational amplifier integrator stage and having an output lead serving as said output terminal of said electronic gain-integrator stage; and

an integrator capacitor having a first plate connected to said inverting input lead of said operational amplifier of said operational amplifier integrator stage and having a second plate for connection to said output lead of said first buffer amplifier.

8. The structure as in claim 7 wherein said means for applying includes a means for producing a voltage equal to said offset voltage of said operational amplifier integrator stage, said means for producing comprising:

a second buffer amplifier having an input lead and an output lead;

a storage capacitor having a first plate connected to a reference voltage and a second plate connected to said input lead of said second buffer amplifier;

means for connecting said inverting input lead of said operational amplifier of said operational amplifier integrator stage to said output lead of said first buffer amplifier, thereby placing said operational amplifier integrator stage in the unity gain mode, thereby generating on said output lead of said operational amplifier of said operational amplifier integrator stage said offset voltage of said operational amplifier integrator stage; and

switch means for connecting said second plate of said storage capacitor to said output lead of said operational amplifier of said operational amplifier integrator stage when said integrator stage is in the unity gain mode, and for producing on said output lead of said second buffer amplifier a voltage equal to said offset voltage of said operational amplifier integrator stage when said operational amplifier integrator stage is not in the unity gain mode.

9. The structure as in claim 8 wherein said means for applying further comprises:

an input capacitor having a first and a second plate;

a first switch means connected between said output lead of said Mth operational amplifier gain stage and said first plate of said input capacitor;

a second switch means connected between said first plate of said input capacitor and a reference voltage;

a third switch means connected between said second plate of said input capacitor and said output lead of said second buffer amplifier; and

a fourth switch means connected between said second plate of said input capacitor and said input lead of said operational amplifier integrator stage;

means for operating said first, second, third, and fourth switch means wherein;

during a first period said first and said third switch means are closed and said second and said fourth switch means are open, thereby storing on said input capacitor a voltage equal to said error component, which is produced in response to said initialization of said M gain stages, minus said offset voltage of said operational amplifier integrator stage;

during a second period said first and said third switch means are open and said second and said fourth switch means are closed, thereby storing on said input capacitor a voltage equal to the negative of said offset voltage of said operational amplifier integrator stage,

said first and second period occuring during said first half of said selected cycle such that the negative of said error component, which is produced in response to the initialization of said M gain stages, is integrated on said integrator capacitor and that the effects of said offset voltage of said operational amplifier integrator stage are eliminated;

during a third period said first and fourth switch means are open and said second and third switch means are closed, thereby storing on said input capacitor a voltage equal to the negative of said offset voltage of said operational amplifier integrator stage; and

during a fourth period said second and third switch means are open and said first and fourth switch means are closed, thereby storing on said input capcitor a voltage equal to the positive of said error component, which is produced in response to said input signals, plus the positive of said input signal multiplied by each of said programmable gains of each of said M gain stages, minus said offset voltage of said operational amplifier integrator stage, and

said third and fourth period occuring during said second half of said selected cycle such that the positive of said error component, which is produced in response to said input signal, and the positive of said input signal multiplied by each of said programmable gains of each of said M gain stages is integrated on said integrator capacitor and that the effects of said offset voltage of said operational amplifier integrator stage are eliminated.

10. The method of eliminating the effects of the offset voltages of a gain-integrator stage which includes an operational amplifier integrator stage and a plurality of operational amplifier gain stages, where M is a selected positive integer, which comprises the steps of:

initializing said operational amplifier integrator stage, thereby producing an inherent offset voltage;

initializing said M operational amplifier gain stages, thereby producing a first output signal, which is a function of the inherent offset voltages of each operational amplifier gain stage;

storing said first output signal minus said offset voltage of said operational amplifier integrator stage on an input capacitor;

storing the negative of said offset voltage of said operational amplifier integrator stage on said input capacitor, thereby integrating the negative of said first output signal of said operational amplifier gain stages and eliminating the effects of said offset voltage of said operational amplifier integrator stage;

storing said offset voltage of said operational amplifier integrator stage on said input capacitor;

applying an input signal to said operational amplifier gain stages, thereby producing a second output signal which is a function of said offset voltages of said operational amplifier gain stages, of said input signal, and the gain of each said operational amplifier gain stage; and

storing on said input capacitor of said second output signal minus said offset voltage of said operational amplifier integrator stage, thereby integrating said second output signal on said integrating capacitor and eliminating the effects of said offset voltage of said operational amplifier integrator stage, thereby eliminating the effects of said offset voltage of operational amplifier gain stages.