Interruptable microprogram controller for microcomputer systems

• US 4,438,492 A
• Filed: 08/01/1980
• Issued: 03/20/1984
• Est. Priority Date: 08/01/1980
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Harmon, William J. Jr., Mick, John R., Coleman, Vernon
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Rutherford, D.
• Application Number:
  US06/174,323
• Time in Patent Office: 1,327 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/244
• CPC Class Codes: G06F 9/268 Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs

Abstract

A microprogram controller, in a microcomputer system used as an address sequencer intended for controlling the sequence of execution of microinstructions in a microprogram memory, is presented. The microprogram controller includes architecture that provides the capability to asynchronously receive indications of an event, break from the microinstruction sequence in response, branch to control of subroutine consisting of a predetermined microinstruction sequence directed to responding to the event, and returning to the interrupted sequence upon completion of the subroutine.

Claims

1. A microprogram controller having output means for generating through said output means microinstruction address signals used to access a program memory element containing a plurality of microinstructions, there being a first register means connected to said memory element for receiving and temporarily holding microinstructions accessed from said memory element by said microinstruction address signals and bus means for communicating a portion of said accessed microinstruction from said first register means to said microprogram controller, said microprogram controller comprising:

input means connected to said bus means for receiving instruction words and data words;

decode means connected to said input means for receiving said instruction words to generate therefrom a plurality of control signals;

first address generating means, having second register means and incrementing means operably interconnected to provide sequentially incremented address signals;

storage means responsive to said control signals for selectively storing address signals; and

first multiplex means, connected to said input means, said first address generating means and said storage means, for selectively coupling said input means, said first address generating means, and said storage means to said output means in response to said control signals, said first address generating means and said storage means further connected to a first multiplex output terminal means for receiving signals therefrom in response to said control signals;

whereby said microinstruction address signals are generated.

2. The microprogram controller of claim 1, wherein said microprogram controller is responsive to an interrupt signal said microprogram controller further comprising interrupt means for receiving said interrupt signal and for generating therefrom gating signals that inhibit communication of the next sequential address signals to be generated through said output means and to cause to be stored said next sequential address signals in said storage means, said interrupt means including means for generating interrupt address signals and for communicating said interrupt address signals to said memory element.

3. The microprogram controller of claim 2, wherein said interrupt means includes means for determining the number of address signals stored in said storage means and for inhibiting response said interrupt signal upon a predetermined number of said address signals stored in said storage means.

4. The microprogram controller of claim 2, wherein said interrupt address generating means includes latch means coupled to said input means for receiving and temporarily holding said interrupt address signals, said second multiplex means including means for selectively coupling said latch means to said output means in response to said gating signals.

5. The microprogram controller of claim 2 further connected to a second memory element containing a plurality of interrupt addresses and means for selecting a predetermined one of said interrupt addresses when said interrupt signal is generated, wherein said interrupt means includes means for enabling said predetermined interrupt address to be accessed from said second memory element to provide said interrupt address signals at said output means.

6. The microprogram controller of claim 5, wherein said microprogram controller further comprises interrupt address incrementing means connected to said output means for receiving and incrementing said predetermined interrupt address signals, and for communicating said incremented interrupt address signals to said second register means.

7. The microprogram controller of claim 1 further comprising second multiplex means connected between said multiplex means and said output means, for selectively coupling said first multiplex means to said output means.

8. The microprogram controller of claim 7, wherein said microprogram controller is responsive to an interrupt signal;

and wherein said microprogram controller further comprises means for receiving said interrupt signal and for generating therefrom gating signals that inhibit communication of the next sequential address to said output means and to cause to be stored the next sequential address signals to be generated through said output means and to cause to be stored said next sequential address signals in said storage means, said interrupt means including means for generating interrupt address signals and for communicating said interrupt address signals to said memory element.

9. A microprogram controller having output means for generating through said output means microinstruction address signals used to access a program memory element containing a plurality of microinstructions, there being a first register means connected to said memory element for receiving and temporarily holding a microinstruction accessed from said memory element by said microinstruction address signals and bus means for communicating a portion of said microinstruction from said first register means to said microprogram controller, said microprogram controller comprising:

input means connected to said bus means for receiving instruction words and data words;

decoder means connected to said input means for receiving said instruction words to generate therefrom a plurality of control signals;

first address generating means to provide sequentially incremental address signals from received address signals;

storage means responsive to said control signals for selectively storing address signals;

first multiplex means, connected to said input means, said first address generating means and said storage means, for selectively coupling said input means, said first address generating means and said storage means to an output terminal means; and

second register means connected to said first multiplex output terminal means for temporarily holding address signals from said first multiplex means, and for providing address signals to said first address generating means and to said output means;

whereby, while said first register means holds the microinstruction of a first address signals, said microprogram controller in operation holds the next sequential address signals in said second register means and forms the third sequential address signals through said first multiplex means.

10. The microprogram controller of claim 9, wherein said microprogram controller is responsive to an interrupt signal;

and wherein said microprogram controller further comprises means for receiving said interrupt signal and for generating therefrom gating signals that inhibit communication of the next sequential address to said output means and to cause to be stored the next sequential address signals to be generated through said output means and to cause to be stored said next sequential address signals in said storage means, said interrupt means including means for generating interrupt address signals and for communicating said interrupt address signals to said memory element.