Apparatus of fault-handling in a multiprocessing system

• US 4,438,494 A
• Filed: 08/25/1981
• Issued: 03/20/1984
• Est. Priority Date: 08/25/1981
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Johnson, David B., Hosler, Brad W., Carson, David G., Peterson, Craig B., Cornish, Anthony L., Budde, David L.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Fleming, Michael R.
• Application Number:
  US06/296,025
• Time in Patent Office: 938 Days
• Field of Search: 364/200, 364/900, 371/11
• US Class Current: 714/2
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0784 Routing of error reports, e.g. with a specific transmission path or data flow
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

A number of intelligent crossbar switches (100) are provided in a matrix of orthogonal lines interconnecting processor (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding error-reporting lines (106); and memory buses (107) with corresponding error-reporting lines (108). At the intersection of these lines is a crossbar switch node (100). The crossbar switches function to pass memory requests from a processor to a memory module attached to an MCU node and to pass any data associated with the requests. The system is organized into confinement areas at the boundaries of which are positioned error-detection mechanisms to deal with information flow occurring across area boundaries. Each crossbar switch and MCU node has means for the logging and signaling of errors to other nodes. Means are provided to reconfigure the system to reroute traffic around the confinement area at fault and for restarting system operation in a possibly degraded mode.

Claims

1. In a data processing system in which a switching matrix provides electrical interconnections between horizontal MACD buses and vertical ACD buses connected in said matrix by means of nodes, a fault-handling mechanism comprising:

an error-reporting matrix including horizontal Bus Error Report Lines (BERLs) and vertical Module Error Report Lines (MERLs),

said BERLs being associated with said MACD buses such that all nodes sharing an MACD bus are connected with a BERL,

said MERLs being associated with said ACD buses such that all nodes sharing an ACD bus are connected with a MERL; and

,

error-reporting means connected at the intersection of one of said MERLs and one of said BERLs,

said error-reporting means including receiving means connected to said MERL for receiving first error messages, said first error messages being transmitted over said one MERL,

said error-reporting means further including propagating means connected to said receiving means and said one BERL, responsive to said receiving means for propagating second error messages over said one BERL to other error-reporting means located at said other nodes in said matrix.

2. The combination in accordance with claim 1 wherein said data processing system further includes memory means, said memory means including a memory control unit;

said memory control unit being connected to at least one of said BERLs and at least one of said MACD buses, said one MACD bus including data lines for carrying bits representing a data field and address lines for carrying bits representing an address field;

said memory control unit including address logic for registering said address field bits, data logic for registering said data field bits, and error detection means,

said error detection means having inputs connected to said address logic and said data logic and an output connected to said MACD bus,

said error detection means including means utilizing said data bits and said address bits for generating an error correcting code checksum on said output thereof,

said checksum providing error detection for failures in said address lines as well as failures in said data lines; and

means in said memory control unit connected to said address logic means and said data logic means, responsive to said error detection means output, for storing said data field and said checksum at a memory location in said memory means specified by said address field.

3. The combination in accordance with claim 1 further comprising:

a memory control unit;

said memory control unit being physically connected to two MACD buses, each bus having two BERL lines associated therewith;

said memory control unit including switching means for switching logical connection to said buses;

said memory control unit being logically connected, by actuation of said switching means by said memory control unit in response to an error or by external command, to only one selected MACD bus at a time, one MACD bus being denoted primary bus and the other MACD bus being denoted backup bus for said memory control unit;

said memory control unit including means for reporting errors on the two BERL lines associated with said selected bus;

said memory control unit including first logic means responsive to an error occurrence or a command for activating said switching means to switch buses in response to the detection of an error or in response to a command and,

said memory control unit including second logic means for preventing the removal of more than one BERL from service, so that the loss of BERLs does not prevent errors from being correctly reported.

4. The combination in accordance with claim 1 wherein said error-reporting means further comprises:

error detection means for detecting the occurrence of an error;

reporting means, connected to said error-detection means and to said BERL, responsive to the detection of an error, for sending an error-report message on said BERL;

first means, connected to said BERL, responsive to an error-report message received over said BERL, for rebroadcasting said message (the report message from BERL) on said MERL to thereby inform error-reporting means at other nodes of said error-reporting matrix that an error has occurred;

second means, connected to said MERL, responsive to the receipt of a complete error-report message over MERL, for rebroadcasting said message (the report message from MERL) over said BERL to thereby initiate the logging of an error at said other nodes; and

,

logging means connectd to said BERL, responsive to said error-report message for logging said error-report message.

5. The combination in accordance with claim 4 wherein said error-reporting means further comprises:

arbitration means, connected to said error detection means and responsive to the detection of simultaneous multiple errors, for determining which error will be logged throughout the system,

said arbitration means including a primary arbitration mechanism which orders said errors on a first-come, first-served basis and a secondary arbitration mechanism which orders said errors by error types and node identification.

6. The combination in accordance with claim 5 wherein said primary arbitration mechanism further comprises:

first inhibiting means, connected to said BERL, for inhibiting the rebroadcast of an error-report message if another error-report message is in progress on an error-report line; and

,

second inhibiting means connected to said MERL and said BERL, activated upon the condition that error reports are received over said BERL and said MERL at the same time, for inhibiting the report on said BERL.

7. In a data processing system in which a switching matrix provides electrical interconnections between horizonal MACD buses and vertical ACD buses connected in said matrix by means of nodes, and in which a fault-handling mechanism provides an error-reporting matrix including horizontal Bus Error Report Lines (BERLs) and vertical Module Error Report Lines (MERLs), said BERLs being associated with said MACD buses such that all nodes sharing an MACD bus are connected with a BERL so that errors occurring in error confinement areas may be rebroadcast over one of said BERLs, said MERLs being associated with said ACD buses such that all nodes sharing an ACD bus are conneted with a MERL so that errors occurring in error-confinement areas may be reported over a corresponding one of said MERLs;

error-report log means connected at the intersection of one of said MERLs and one of said BERLs comprising;

holding means connected to said MERLS and said BERLS for holding information from a most recent error-report message;

logging means connected to said holding means for logging error reports, said logging means including means for uniquely identifying said error reports so that said error reports are distinguishable as between the single occurrence of an error, and repeated occurrences of the same error; and

,

logic means connected to said holding means and said logging means for immediately updating said logging means upon te condition that an error-report message is received, said logic means including an error-count means, and means connected to said error-count means for incrementing said error count means upon the condition that the single occurrence of an error is reported.

8. The combination in accordance with claim 7 wherein said error-report log means further comprises:

means for read-accessing the log contents of said logging means at a first time and at a second time that is subsequent to said first time;

first means for storing said log contents of said logging means read at said first time to provide a previous log count field;

second means for storing said log contents of said loging means read at said first time to provide a current log count field; and

,

comparing means connected to said first and second means for comparing said previous count field stored in said first means with said current count field stored in said second means,

said comparing means including means operative upon the condition that the count-field contents are identical, for indicating that no error has occurred, and operative upon the condition that the count-field contents are different, for indicating that a new error(s) has occurred, to thereby allow the identification of new errors without requiring that all logs in the system be cleared after each error occurrence.

9. In a data processing system in which a switching matrix provides electrical interconnections between horizontal MACD buses and vertical ACD buses connected in said matrix by means of nodes, and in which a fault-handling mechanism provides an error-reporting matrix including horizontal Bus Error Report Lines (BERLs) and vertical Module Error Report Lines (MERLs), said BERLs being associatd with said MACD buses such that all nodes sharing an MACD bus are connected with a BERL so that errors occurring in error-confinement areas may be reported over one of said BERLs, said MERLs being associated with said ACD buses such that all nodes sharing an ACD bus are connected with a MERL so that errors occurring in error-confinement areas may be rebroadcast over one of said MERLs;

error-reporting logic testing means at one node connected at the intersection of one of said MERLs and one of said BERLs comprising;

test command receiving means connected to said MACD bus for receiving a test command;

said test command including means which identifies said one node as a node (tested node) to be tested,

said test command being comprised of a read access request for read data from said one node, said read access request being directed to said one node (tested node) from another node (testing node) over said MACD bus; and

,

test logic means connected to said test command receiving means and to said MACD bus, responsive to said test command receiving means, for returning said read data to said testing node;

said test logic means including means for causing a known error condition to occur in said read data, thereby forcing an error at one of said confinement areas.

10. The combination in accordance with claim 9 wherein said test logic means further comprises:

means for generating an error report message on said BERL; and

, wherein said testting node includes;

logging means at said testing node;

means at said testing node connected to said logging means at said testing node, for causing said error-report message received on said BERL to be logged in said logging means at said testing node; and

,

means at said testing node responsive to said logging means at said testing node, for reporting a module error upon the condition that said logged error-report message does not contain a reported error.