Apparatus for recognition of stylized characters

• US 4,441,204 A
• Filed: 12/02/1981
• Issued: 04/03/1984
• Est. Priority Date: 12/15/1980
• Status: Expired due to Term

• Current Assignee: Compagnie Internationale Pour L'Informatique A Corporation France
• Original Assignee: Compagnie Internationale Pour L'Informatique Cii-Honeywell Bull
• Inventors: Hanna, Charas
• Primary Examiner(s): Martin, John C.
• Assistant Examiner(s): Parker, Michael D.
• Application Number:
  US06/326,702
• Time in Patent Office: 853 Days
• Field of Search: 382/7, 382/27, 382/29, 382/33, 382/64, 382/37, 382/57, 235/449, 235/493, 235/494
• US Class Current: 382/139
• CPC Class Codes: G06V 30/2253 Recognition of characters printed with magnetic ink G06V30/2247 takes precedence

Abstract

Character recognition apparatus for the recognition of stylized E13B characters are provided wherein the siganls resulting from the reading of a character by a reading head 17 are sampled to be treated by two different asemblies (EB1 and EB2) of operator-generator blocks of logic signals. The discrimination of the signals delivered by each of these assemblies is realized, in a respective one of the two assemblies (RK1 and RK2) by identification elements (EK1, EK2, . . . , EK14) under the control of two groups of validation circuits (CV1 and CV2). These identification elements (EK1, EK2, . . . , EK14) are each associated with a respective one of the characters of a group.

Claims

1. Character recognition apparatus for the recognition of stylized characters on a document, wherein the characters to be recognized are a part of a group comprising K different characters, a reading station (17, 18, 20) for reading the characters, driving means (13, 14) to cause a relative displacement between the document and said station, in a direction of displacement permitting each character to pass before said reading station, said station including reading means disposed such that each time a character passes before it, the character is read, and a group of N elementary analogic signals is generated, each resulting from the reading of a respective one of N portions of a character obtained by dividing each character to be read along a direction perpendicular to the direction of displacement;

K operator-generator blocks of logic signals (OG1, OG2, OG3 etc.) to be associated with a respective one of the K characters to be read each of these blocks comprising, on the one hand, N multiplier elements (EM1, EM2, EM3, etc.), each connected to the reading station to receive a respective one of the N elementary analogic signals of a group generated by this station and to multiply this elementary signal by a specific coefficient of said multiplier element;

and a summing element (ES) connected to the N multiplier elements to receive the N elementary signals thus multiplied and delivering at its output a single signal having an amplitude equal to the algebraic sum of the amplitudes of the N multiplied signals, and a generator element for generating a logic circuit connected to said summing element (ES) to receive said single signal, said generator element generating at its output one or the other of two logic signals "1" or "0" in accordance with whether the amplitude of said single signal is positive or not, respectively, the operator-generator blocks being divided in p different assemblies (EB1, EB2), p being a whole number such that;

##EQU9## the specific coefficients of said multiplier elements having a value chosen such that, in response to the reading of a character, the operator-generator block which is associated with this character delivers a logic signal "1", the other operator-generator blocks which appertain to the same assembly as this operator-generator block each delivers a logic signal "0" while, in each of the other assemblies at least two operator-generator blocks each deliver a logic signal "1";

p validation means (CV1, CV2) each associated with a respective one of the p assemblies of operator-generator blocks (EB1, EB2) and each generating in response to the reading of a character, a single validation signal in the case where one only of the operator-generator blocks of the associated assembly delivers a logic signal "1"; and

K character identification elements (EK1, EK2, EK3, etc.) each connected to the output of a respective one of the K operator-generator blocks (OG1, OG2, OG3, etc.), said K identification elements being divided in p different assemblies (RK1, RK2) each associated with a respective one of the p validation means (CV1, CV2), each of these identification elements being connected further to the output of the validation means which is associated with it, and generating a single character recognition signal when it receives at the same time, on the one hand, a validation signal generated by the said validation means, and, on the other hand, a logic signal "1" generated by the operator-generator block to which it is connected.

2. Apparatus for the recognition of characters in accordance with claim 1 further comprising a single "OR" circuit (UE) provided, on one hand, with p inputs connected each to a respective one of the outputs of the p validation means (CV1, CV2), and on the other hand, with an output to which are connected the K character identification elements (EK1, EK2, EK3, etc), the single "OR" circuit being operatively connected to deliver at its output a single binary signal "1" in the case where one only of the p validation means engenders a validation signal, each of the K identification elements further generating a character recognition signal in response to the simultaneous reception of a validation signal and of a logic signal "1" only if it also receives a binary signal "1" from the single "OR" circuit.

3. Apparatus for the recognition of characters in accordance with claim 2, further comprising indicator rejection means (IR) connected to the output of the single "OR" circuit (UE) to deliver at its output a signal indicating rejection of the character read by the reading station, in the case where the single "OR" circuit does not deliver the binary signal "1".

4. Apparatus for the recognition of characters in accordance with claim 2, wherein each identification element is constituted by an "AND" circuit with three inputs of which the first is connected to the output of the operator-generator block which is associated with this element of which the second is connected to the output of the validation means associated with said element and of which the third is connected to the output of the single "OR" circuit (UE).

5. Apparatus for the recognition of characters in accordance with claims 1, 2, 3 or 4 wherein the p assemblies of operator-generator blocks are formed of (p-1) assemblies each comprising N operator-generator blocks and of a p^th assembly comprising (K+N-pN) operator-generator blocks, the p validation means include:

(p-1) first validation means each associated with a respective one of (p-1) said assemblies of operatoar-generator blocks and each comprising, on the one hand, N "AND" circuits (E1, E2, E3, etc.) each associated with a respective one of the operator-generator blocks (OG1, OG2, OG3, etc.) of the associated assembly and each having N inputs of which one is connected to the output of the operator-generator block associated with it and of which the others are each connected through an inverter circuit (I1, I2, I3, etc.) to a respective one of the outputs of the other operator-generator blocks of the associated assembly, on the other hand, an "OR" circuit (U1) having N inputs each connected to a respective one of the outputs of the N "AND" circuits; and

a p^th means of validation comprising, on the one hand, (K+N-pN) "AND" circuits each associated with a respective one of the operator-generator blocks of the p^th assembly and each possessing (K+N-pN) inputs of which one is connected to the output of the associated operator-generator block and of which the others are each connected, through an inverter circuit, with a respective one of the outputs of the other operator-generator blocks of the p^th assembly, and on the other hand, an "OR" circuit having (K+N-pN) inputs connected each to a respective one of said outputs (K+N-pN) of the "AND" circuits.

6. Apparatus for the recognition of characters in accordance with claim 5, wherein each of the p and p^th validation means further comprise a second "OR" circuit (UGI) which in one of the (p-1) first validation means comprises N inputs each connected to a respective one of the outputs of the operator-generator blocks (OG1 to OG7) of the associated assembly, and in the p^th validation means comprises (K+N-pN) inputs connected each to a respective one of the outputs of the operator blocks of the p^th assembly, each of the first "OR" circuits of the p validation means further comprising p supplementary inputs each connected, through an inverter circuit, to a respective one of the outputs of the said p second "OR" circuits.

7. Apparatus for recognition of characters in accordance with any of the claims 1, 2, 3 or 4 wherein each generator block is an operational amplifier (AP), and the reading station (17, 18, 20) comprises N outputs (M1, M2, M3, etc.) each to deliver a respective one of the N elementary signals resulting from the reading of the character, each of the N outputs of this station being connected, through a respective one of N resistances (R1, R2, R3, etc.), either to the inverting input (-), or to the noninverting input (+) of said amplifier, whereby the sign of the signal delivered by said output will or will not be inverted, the values of the N resistances as well as the manner of connection of said outputs on the two inputs of this amplifier being such that, when the character read is that which is associated with said operator block, the amplitude of the signal delivered at the output of said amplifier is practically equal to +1 volt.

8. Apparatus for recognition of characters in accordance with claim 5 wherein each generator block is an operational amplifier (AP), and the reading station (17, 18, 20) comprises N outputs (M1, M2, M3, etc.) each to deliver a respective one of the N elementary signals resulting from the reading of the character, each of the N outputs of this station being connected, through a respective one of N resistances (R1, R2, R3, etc.), either to the inverting input (-), or to the noninverting input (+) of said amplifier, whereby the sign of the signal delivered by said output will or will not be inverted, the values of the N resistances as well as the manner of connection of said outputs on the two inputs of this amplifier being such that, when the character read is that which is associated with said operator block, the amplitude of the signal delivered at the output of said amplifier is practically equal to +1 volt.

9. Apparatus for recognition of characters in accordance with claim 6 wherein each generator block is an operational amplifier (AP), and the reading station (17, 18, 20) comprises N outputs (M1, M2, M3, etc.) each to deliver a respective one of the N elementary signals resulting from the reading of the character, each of the N outputs of this station being connected, through a respective one of N resistances (R1, R2, R3, etc.), either to the inverting input (-), or to the noninverting input (+) of said amplifier, whereby the sign of the signal delivered by said output will or will not be inverted, the values of the N resistances as well as the manner of connection of said outputs on the two inputs of this amplifier being such that, when the character read is that which is associated with said operator block, the amplitude of the signal delivered at the output of said amplifier is practically equal to +1 volt.

10. Apparatus for the recognition of characters in accordance with any one of claims 1, 2, 3 or 4 wherein the reading station (17, 18, 20) includes a reading head (17) of which the output is connected to the input of an analogic delay line (20) having N median contacts each delivering a respective one of N elementary analogic signals, and further comprising K control gates (C1, C2, C3 etc.) each connected to the output of a respective one of K character identification elements (EK1, EK2, EK3, etc.), and a supplementary validation means (AD, CK, BIK, R1, R2) connected between the control gates (C1, C2, C3 etc.) and the delay line (20) to deliver to said gates a control signal for releasing the transfer to the utilization members D1, D2, D3 etc.) of the recognition signal created by the K identification elements, said control signal being generated only when the N elementary analogic signals resulting from the reading of a character appear simultaneously on the N median contacts.

11. Apparatus for the recognition of characters in accordance with claim 5 wherein the reading station (17, 18, 20) includes a reading head (17) of which the output is connected to the input of an analogic delay line (20) having N median contacts each delivering a respective one of N elementary analogic signals, and further comprising K control gates (C1, C2, C3 etc.) each connected to the output of a respective one of K character identification elements (EK1, EK2, EK3, etc.), and a supplementary validation means (AD, CK, BIK, R1, R2) connected between the control gates (C1, C2, C3 etc.) and the delay line (20) to deliver to said gates a control signal for releasing the transfer to the utilization members (D1, D2, D3 etc.) of the recognition signal created by the K identification elements, said control signal being generated only when the N elementary analogic signals resulting from the reading of a character appear simultaneously on the N median contacts.

12. Apparatus for the recognition of characters in accordance with claim 6 wherein the reading station (17, 18, 20) includes a reading head (17) of which the output is connected to the input of an analogic delay line (20) having N median contacts each delivering a respective one of N elementary analogic signals, and further comprising K control gates (C1, C2, C3 etc.) each connected to the output of a respective one of K character identification elements (EK1, EK2, EK3, etc.), and a supplementary validation means (AD, CK, BIK, R1, R2) connected between the control gates (C1, C2, C3 etc.) and the delay line (20) to deliver to said gates a control signal for releasing the transfer to the utilization members (D1, D2, D3 etc.) of the recognition signal created by the K identification elements, said control signal being generated only when the N elementary analogic signals resulting from the reading of a character appear simultaneously on the N median contacts.

13. Apparatus for the recognition of characters in accordance with claim 7 wherein the reading station (17, 18, 20) includes a reading head (17) of which the output is connected to the input of an analogic delay line (20) having N median contacts each delivering a respective one of N elementary analogic signals, and further comprising K control gates (C1, C2, C3 etc.) each connected to the output of a respective one of K character identification elements (EK1, EK2, EK3, etc.), and a supplementary validation means (AD, CK, BIK, R1, R2) connected between the control gates (C1, C2, C3 etc. and the delay line (20) to deliver to said gates a control signal for releasing the transfer to the utilization members (D1, D2, D3 etc.) of the recognition signal created by the K identification elements, said control signal being generated only when the N elementary analogic signals resulting from the reading of a character appear simultaneously on the N median contacts.