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Apparatus for recognition of stylized characters

  • US 4,441,204 A
  • Filed: 12/02/1981
  • Issued: 04/03/1984
  • Est. Priority Date: 12/15/1980
  • Status: Expired due to Term
First Claim
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1. Character recognition apparatus for the recognition of stylized characters on a document, wherein the characters to be recognized are a part of a group comprising K different characters, a reading station (17, 18, 20) for reading the characters, driving means (13, 14) to cause a relative displacement between the document and said station, in a direction of displacement permitting each character to pass before said reading station, said station including reading means disposed such that each time a character passes before it, the character is read, and a group of N elementary analogic signals is generated, each resulting from the reading of a respective one of N portions of a character obtained by dividing each character to be read along a direction perpendicular to the direction of displacement;

  • K operator-generator blocks of logic signals (OG1, OG2, OG3 etc.) to be associated with a respective one of the K characters to be read each of these blocks comprising, on the one hand, N multiplier elements (EM1, EM2, EM3, etc.), each connected to the reading station to receive a respective one of the N elementary analogic signals of a group generated by this station and to multiply this elementary signal by a specific coefficient of said multiplier element;

    and a summing element (ES) connected to the N multiplier elements to receive the N elementary signals thus multiplied and delivering at its output a single signal having an amplitude equal to the algebraic sum of the amplitudes of the N multiplied signals, and a generator element for generating a logic circuit connected to said summing element (ES) to receive said single signal, said generator element generating at its output one or the other of two logic signals "1" or "0" in accordance with whether the amplitude of said single signal is positive or not, respectively, the operator-generator blocks being divided in p different assemblies (EB1, EB2), p being a whole number such that;

    ##EQU9## the specific coefficients of said multiplier elements having a value chosen such that, in response to the reading of a character, the operator-generator block which is associated with this character delivers a logic signal "1", the other operator-generator blocks which appertain to the same assembly as this operator-generator block each delivers a logic signal "0" while, in each of the other assemblies at least two operator-generator blocks each deliver a logic signal "1";

    p validation means (CV1, CV2) each associated with a respective one of the p assemblies of operator-generator blocks (EB1, EB2) and each generating in response to the reading of a character, a single validation signal in the case where one only of the operator-generator blocks of the associated assembly delivers a logic signal "1"; and

    K character identification elements (EK1, EK2, EK3, etc.) each connected to the output of a respective one of the K operator-generator blocks (OG1, OG2, OG3, etc.), said K identification elements being divided in p different assemblies (RK1, RK2) each associated with a respective one of the p validation means (CV1, CV2), each of these identification elements being connected further to the output of the validation means which is associated with it, and generating a single character recognition signal when it receives at the same time, on the one hand, a validation signal generated by the said validation means, and, on the other hand, a logic signal "1" generated by the operator-generator block to which it is connected.

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