Dynamically buffered data transfer system for large capacity data source

• US 4,442,485 A
• Filed: 12/05/1980
• Issued: 04/10/1984
• Est. Priority Date: 12/07/1979
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ota, Hideo, Kubo, Yutaka
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Williams, Jr., Archie E.
• Application Number:
  US06/213,403
• Time in Patent Office: 1,222 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/455, 370/104, 455/12, 455/13
• US Class Current: 710/57
• CPC Class Codes: G06F 13/122 where hardware performs an I/O function other than control of data transfer
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06T 1/0007 Image acquisition

Abstract

A data input/output system is provided for transfer of data between a large capacity data source and a large-capacity memory. The data input/output control information is supplied from a processor. If the actual time between input/output information units from the large-capacity data source is shorter than that time determined by a program in the processor, an interruption signal is generated to be in time for the input/output timing of the next input/output data unit. The system permits continuous data transfer switching from one input/output data unit to the next input/output data unit without use of the program in the processor.

Claims

1. A data input/output method for transferring data between a large-capacity data source and a large-capacity memory connected to a processor by means of at least two buffer memories connected to said processor through an input/output bus, wherein the data transfer on the input/output bus is controlled by input/output control information decoded by a control section, said processor supplying a control register with said input/output control information having a command, a data count, a data address and a next-command address, comprising the steps of:

transmitting said input/output control information from said control register to said control section to be decoded therein;

supplying said control register with second input/output information from said next-command address in said input/output control information after said transmitting step;

transferring data up to the amount of said data count in said input/output control information through said input/output bus from or to one of said buffer memories on the basis of a result of said decoding;

transmitting said second input/output information from said control register to said control section to be decoded therein after said data transfer; and

transferring data in accordance with said second input/output information from or to the other of said buffer memories.

2. A data input/output method in accordance with claim 1 further including the step of:

circulating said input/output information in accordance with said next-command address included therein toward said second input/output information so as to specify a portion of said second input/output information.

3. A data input/output method in accordance with claim 2 further comprising the step of:

applying an interruption after said data transferring step from said control section to said processor responding to a flag set by a program in said processor, thereby to achieve either ending the data transfer or renewing any input/output information.

4. A data input/output system comprising:

(a) a large-capacity data source;

(b) a processor including means for processing data from said large-capacity data source;

(c) a buffer memory including means for temporarily storing data from said large-capacity data source;

(d) a large-capacity memory including means for storing data from said buffer memory;

(e) data input/output controller means responsive to receipt from said processor of input/output control information for controlling data transfer between said large capacity data source and said buffer memory; and

(f) a data transfer input/output bus connected to said processor, said large-capacity memory, said data input/output controller means, said large-capacity data source and said buffer memory;

(g) said processor further including storage means in the form of a circular table wherein input/output control information is stored, said control information including an address for specifying successive control information circularly in said storage means and at least a first flag for indicating an interrupt condition;

(h) said input/output means including means for generating a first interruption signal to said processor so as to cause said processor to renew the control information in said circular table if said first flag is set in said control information.

5. A data input/output system according to claim 4 wherein said data input/output controller includes control register means for storing said control information from said processor while said data input/output controller controls said data transfer.

6. A data input/output system according to claim 4 wherein said data input/output controller includes means for generating a second interruption signal to said processor so as to end said data transfer if a second flag is set by said processor.

7. A data input/output system according to claim 4 further comprising a histograming apparatus connected to said transfer input/output bus, wherein said data from said large-capacity data source is image data, comprising:

a plurality of counters having an address input for each of said counters, and

a counter address encoder for encoding an image element included in said image data so as to output an encoded address,

wherein a counter specified by said encoded address counts up while said data is transferred through said data transfer input/output bus.

8. A method of controlling the transfer of data between a large-capacity data source and a buffer memory by means of a bus in response to a control program having a plurality of sets of control information, each set including at least a command, a data count value, a data address, a next-command address and a flag bit, comprising the steps of:

(1) storing in a storage device a plurality of sets of control information relating to a program for transferring data from said large capacity data source into said buffer memory via said bus;

(2) reading out a first set of control information from said storage device to a control register;

(3) decoding said first set of control information in said control register, including determining whether the flag bit is set therein;

(4) if said flag bit of said first set of control information is set, reading out a second set of control information from the storage location in said storage device identified by the decoded next-command address of said first set into said control register and executing the decoded command of said first set by controlling said bus to effect the transfer of successive data elements in number corresponding to the decoded data count value of said first set from said large-capacity data source to the data address in said buffer memory decoded from said first set of control information;

(5) repeating steps (1) through (4) for further sets of control information in said storage device until it is detected in a decoded set of control information that the flag bit is not set; and

(6) selectively resetting the flag bit in any one of the plurality of sets of control information stored in said storage device.

9. A method according to claim 8 wherein each set of control information includes a second flag bit and said decoding step (3) includes determining whether said second flag bit is set, further including the steps of:

(7) if said second flag bit is set, renewing at least some of the sets of control information stored in said storage device as to the data count value, data address and/or next-command address thereof; and

(8) selectively setting said second flag bit in any one of the plurality of sets of control information stored in said storage device.

10. A method according to claim 8, wherein said storage device is in the form of a circular table in which successive sets of control information are stored at successive storage locations.

11. A method according to claim 8, wherein each set of control information includes a second flag bit and said decoding step (3) includes determining whether said second flag bit is set, further including the steps of:

(7) if said second flag bit is set, transferring data out of said buffer memory to a large capacity memory; and

(8) selectively setting said second flag bit in any one of the plurality of sets of control information stored in said storage device.

12. A method according to claim 8 wherein each set of control information includes a second flag bit and an interruption designation which identifies a first or a second type of interruption, and said decoding step (3) includes determining whether said second flag bit is set, further including the steps of:

(7) if said second flag bit is set and said interruption designation indicates a first type of interruption, renewing at least some of the sets of control information stored in said storage device as to the data count value, data address and/or next-command address thereof;

(8) if said second flag bit is set and said interruption designation indicates a second type of interruption, transferring data out of said buffer memory to a large capacity memory; and

(9) selectively setting said second flag bit and said interruption designation in any one of the plurality of sets of control information stored in said storage device.

13. A system for controlling the transfer of data from a large-capacity data source to a buffer memory via a bus in response to a control program having a plurality of sets of control information, each set including at least a command, a data count value, a data address, a next-command address and a flag bit, comprising:

a processor connected to said bus and including said buffer memory, said storage means, means for processing data from said large-capacity data source, and means for initiating transfer of data from said large-capacity data source to said buffer memory by generation of a start signal;

storage means for storing a plurality of sets of control information in addressable storage locations; and

control means connected to said processor and said bus for controlling said bus to effect transfer of data from said large-capacity memory to said buffer memory including register means responsive to said start signal for reading out and storing a first set of control information from said storage means, decoding means connected to said register means for decoding the set of control information stored in said register means, and means responsive to said decoding means for controlling said register means to read out and store another set of control information from the address in said storage means indicated by the decoded next-command address of said first set when the flag bit in the set of control information in said register means is set and for controlling said bus to effect transfer of successive data elements in number corresponding to the decoded data count value of said set of control information in said register means from said large-capacity data source to the decoded data address in said buffer memory derived from said set of control information in said register means.

14. A system according to claim 13, wherein each set of control information in said storage means also includes a second flag bit, and wherein said processor further includes means connected to said decoding means for renewing at least some of the sets of control information in said storage means as to the data count value, data address and/or next-command address thereof when the second flag bit of the set of control information in said register means is set.

15. A system according to claim 13, further including a large capacity memory, and wherein each set of control information in said storage means also includes a second flag bit, and wherein said processor further includes means connected to said decoding means for initiating the transfer of data from said buffer memory to said large-capacity memory when the second flag bit of the set of control information in said register means is set.

16. A system according to claim 13, further including a large-capacity memory, and wherein each set of control information in said storage means also includes a second flag bit and an interruption designation which identifies a first or a second type of interruption, and wherein said processor further includes means connected to said decoding means for renewing at least some of the sets of control information in said storage means when the second flag bit is set and the interruption designation indicates a first type of interruption in the set of control information in said register means and for initiating the transfer of data from said buffer memory to said large-capacity memory when the second flag bit is set and the interruption designation indicates a second type of interruption in the set of control information in said register means.

17. A system according to claim 13, wherein said storage means comprises a storage device in the form of a circular table in which successive sets of control information are stored at successive storage locations.

18. A system according to claim 13, further comprising a histograming means connected to said bus for making a histogram of the data transmitted by said bus.