Electrically programmable read-only memory stacked above a semiconductor substrate

• US 4,442,507 A
• Filed: 02/23/1981
• Issued: 04/10/1984
• Est. Priority Date: 02/23/1981
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Roesner, Bruce B.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/237,428
• Time in Patent Office: 1,142 Days
• Field of Search: 365/94, 365/100, 365/96, 365/103, 365/104, 365/105, 365/227, 365/175
• US Class Current: 365/100
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

In the disclosed memory, address decode means are integrated into a surface of a substrate, for addressing cells in the memory; an insulating layer covers the address decode means and the substrate; an array of spaced-apart memory cell select lines lie on the insulating layer; and outputs from the address decode means respectively couple through the insulating layer to the select lines. Each cell of the memory is comprised of a pair of the select lines and further includes a resistive means between that pair which irreversibly switches from a relatively high resistance state to a relatively low resistance state upon the application of a threshold voltage thereacross, and the resistance states are representative of the information in the cell.

Claims

1. An electrically programmable read only memory having memory cells on an insulating layer which overlies a semiconductor substrate;

each of said memory cells comprising;

a first semiconductor material having a polycrystalline grain structure;

a metallic compound in contact with said first semiconductor material forming a Schottky diode therewith; and

a second semiconductor material serially coupled within said cell to said Schottky diode;

said second semiconductor material consisting essentially of a single element semiconductor selected from the group of Si, Ge, C, and α

-Sn, having a crystalline grain size which is smaller than that of said polycrystalline semiconductor material, and having a concentration of dopant atoms of less than 10¹⁷ atoms/cm³ ;

whereby said second semiconductor material will exhibit a high resistance that will irreversibly switch to a low resistance without the flowing of any metal therethrough upon the application of a threshold voltage thereacross.

2. A memory according to claim 1 wherein said first semiconductor material contains dopant atoms which are substitutionally disposed, and said second semiconductor material contains dopant atoms which are interstitially disposed.

3. A memory according to claim 1 wherein said first semiconductor material is subjected to temperatures of over 600°

C. whereas said second semiconductor material is subjected to temperatures of only less than 600°

C. to achieve their respective relatively large and small grain sizes.

4. A memory according to claim 1 wherein said metallic compound is disposed between and in direct contact with said first semiconductor material and said second semiconductor material.

5. A memory according to claim 1 wherein said first semiconductor material is disposed between and in direct contact with said metallic compound and said second semiconductor material.

6. A memory according to claim 1 wherein said substrate has a major surface, and said first semiconductor material, said metallic compound, and said second semiconductor material are stacked on top of each other essentially perpendicular to said surface.

7. A memory according to claim 1 which further includes:

address decode means, integrated into a surface of said substrate, for generating signals to address said cells in said memory;

a plurality of spaced-apart memory cell select lines on said insulating layer coupled to said memory cells; and

means for coupling said signals from said address decode means through said insulating layer to said memory cell select lines.

8. A memory according to claim 1 wherein said dopant atoms are N-type.

9. A memory according to claim 1 wherein said dopant atoms are P-type.

10. A memory according to claim 1 wherein said second semiconductor material contains essentially no dopant atoms.

11. An electrically programmable memory cell comprising:

a first semiconductor material having a polycrystalline grain structure;

a metallic compound in contact with said first semiconductor material forming a Schottky diode therewith; and

a second semiconductor material forming a Schottky diode therewith; and

a second semiconductor material serially coupled within said cell to said Schottky diode;

said second semiconductor material consisting essentially of a single element semiconductor selected from the group of Si, Ge, C, and α

-Sn, having a crystalline grain size which is smaller than that of said polycrystalline semiconductor material, and having a concentration of dopant atoms of less than 10¹⁷ atoms/cm³ ;

whereby said second semiconductor material will exhibit a high resistance that will irreversibly switch to a low resistance without the flowing of any metal therethrough upon the application of a threshold voltage thereacross.

12. An electrically programmable memory cell comprising:

a pair of spaced apart conductors for applying a threshold voltage thereacross; and

a semiconductor materially serially coupled between said conductors for receiving said threshold voltage;

said semiconductor material consisting essentially of a single element semiconductor selected from the group of Si, Ge, C, and α

-Sn, having a crystalline grain size which is smaller than polycrystalline and having dopant atoms which are interstitial in the crystals and not substitutional;

whereby said semiconductor material will exhibit a high resistance that will irreversibly switch to a low resistance without the flowing of any metal therethrough upon the application of said threshold voltage thereacross.