Two-level priority circuit
First Claim
1. In a digital computer of the type having an instruction address sequencer, clock means for generating CLK 1 and CLK 1 signals, and a memory which receives access requests from a plurality of requesting sources:
- arbitration means connected to receive CLK 1 and CLK 1 and said memory access requests to arbitrate between effectively concurrent requests in synchronism with CLK 1, said arbitration means comprising a first tier connected to receive and store for processing the memory access requests and a second tier connected to the first tier to receive and store for processing the selected requests, the clock means being connected to the arbitration means are such that CLK 1 operates the first tier and CLK 1 operates the second tier, the first tier comprising a plurality of bistable circuits equal in number to the number of requests to be arbitrated, each of said circuits having a data input connected to receive a request, a reset input adapted to be connected to higher priority circuits, a clock input connected to receive CLK 1, and an output connected to a data input of a device in the second tier.
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Abstract
A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.
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Citations
1 Claim
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1. In a digital computer of the type having an instruction address sequencer, clock means for generating CLK 1 and CLK 1 signals, and a memory which receives access requests from a plurality of requesting sources:
- arbitration means connected to receive CLK 1 and CLK 1 and said memory access requests to arbitrate between effectively concurrent requests in synchronism with CLK 1, said arbitration means comprising a first tier connected to receive and store for processing the memory access requests and a second tier connected to the first tier to receive and store for processing the selected requests, the clock means being connected to the arbitration means are such that CLK 1 operates the first tier and CLK 1 operates the second tier, the first tier comprising a plurality of bistable circuits equal in number to the number of requests to be arbitrated, each of said circuits having a data input connected to receive a request, a reset input adapted to be connected to higher priority circuits, a clock input connected to receive CLK 1, and an output connected to a data input of a device in the second tier.
Specification
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- Resources
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Current AssigneeNixdorf Computer Corporation (Atos SE)
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Original AssigneeNixdorf Computer Corporation (Atos SE)
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InventorsGehman, John T.
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Primary Examiner(s)Zache, Raulfe B.
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Application NumberUS06/260,141Time in Patent Office1,079 DaysField of Search364/200 MS File, 364/900 MS File, 364/200US Class Current713/600CPC Class CodesG06F 9/38 Concurrent instruction exec...
