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Processor module for a programmable controller

  • US 4,443,865 A
  • Filed: 10/26/1981
  • Issued: 04/17/1984
  • Est. Priority Date: 10/26/1981
  • Status: Expired due to Term
First Claim
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1. An improved processor for a programmable controller of the type having an I/O interface for connection to a plurality of I/O devices, wherein the processor has first memory means that stores data relating to the status of the I/O devices, wherein the processor also has means for coupling the first memory means and I/O interface enabling transfer of the status data between the first memory means and the I/O interface, and wherein the improvement in the processor comprises:

  • second memory means for storing user program instructions for operating on the status data, wherein each user program instruction includes a two-segment operation code;

    third memory means for storing machine instructions organized in interpreter routines which are associated with corresponding operation codes for respective user program instructions, the third memory means also storing a machine fetch instruction for reading both segments of a selected one of the operation codes; and

    microelectronic processor means having a machine instruction pointer register coupled to the third memory means to generate address signals thereto, and having a stack pointer register that is coupled to the second memory means to generate address signals thereto, the microelectronic processor means generating address signals to the third memory means to read machine instructions, and the microelectronic processor means being responsive to reading the machine fetch instruction stored in the third memory means to generate address signals from the stack pointer register to the second memory means to read the segments of the selected one of the operation codes into its machine instruction pointer register and to thereafter execute the interpreter routine in the third memory means that is pointed to by that operation code.

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