Field effect current mode logic gate

• US 4,445,051 A
• Filed: 06/26/1981
• Issued: 04/24/1984
• Est. Priority Date: 06/26/1981
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Elmasry, Mohamed I.
• Primary Examiner(s): Anagnos, Larry N.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US06/277,629
• Time in Patent Office: 1,033 Days
• Field of Search: 307/448, 307/450, 307/453, 307/468, 307/481, 307/455, 307/530, 307/362, 307/355, 330/253
• US Class Current: 326/115
• CPC Class Codes: H03K 19/09443 using a combination of enhancement and depletion transistors

Abstract

Disclosed is a field effect current mode logic gate comprised of a current source for supplying a constant current, and a differential amplifier having first and second branches for passing respective portions of the constant current. The first branch includes a plurality of parallel-coupled or serially-coupled enhancement field effect transistors having a positive threshold voltage and having respective gates for receiving respective input logic signals; and the second branch includes a depletion field effect transistor having a negative threshold voltage, and a grounded gate. The magnitudes of the current portions in the first and second branches are representative of the magnitude of the input logic signals relative to the positive threshold voltage plus the absolute value of the negative threshold voltage.

Claims

1. A field effect current mode logic gate comprised of:

a field effect current source means for supplying a constant current;

a field effect differential amplifier means having first and second branches coupled between said current source means and a power source means for passing respective portions of said constant current;

said first branch including a plurality of parallel coupled enhancement field effect transistors having a positive threshold voltage and having respective gates for receiving respective input logic signals; and

said second branch including a depletion field effect transistor having a negative threshold voltage and a grounded gate, whereby the magnitudes of said current portions in said first and second branches are representative of the magnitude of said input logic signals relative to said positive threshold voltage plus the absolute value of said negative threshold voltage.

3. A field effect current mode logic gate according to claims 1 or 2 wherein said field effect transistors are metal-oxide-silicon field effect transistors.

4. A field effect current mode logic gate according to claims 1 or 2 wherein said field effect transistors are N-channel field effect transistors.

5. A field effect current mode logic gate according to claims 1 and 2 wherein said field effect transistors are P-channel field effect transistors.

6. A field effect current mode logic gate according to claims 1 and 2 wherein said plurality of enhancement field effect transistors and said depletion field effect transistor together have a speed power product of less than one pico joule.

7. A field effect current mode logic gate according to claims 1 or 2 wherein each enhancement field effect transistor of said plurality has a width/length ratio of at least 25/2.5.

8. A field effect current mode logic gate according to claims 1 and 2 wherein said current source is another depletion field effect transistor having a gate coupled to its source and to said gate of said previously recited depletion field effect transistor.

9. A field effect current mode logic gate according to claims 1 or 2 wherein said current source is another enhancement field effect transistor having a gate for receiving a control signal which initiates said constant current.

10. A field effect current mode logic gate according to claims 1 or 2 and further including an output means for generating output logic signals indicating which of said branches are passing the larger portion of said constant current and having a speed power product of less than two pico joules.

11. A field effect current mode logic gate according to claims 1 or 2 and further including a pair of output means for generating respective output logic signals indicating which of said branches is passing the larger portion of said constant current, with each output means of said pair including a field effect transistor, and with said field effect transistors in said pair of output means having cross-coupled gates.

2. A field effect current mode logic gate comprised of:

a field effect current source means for supplying a constant current;

a field effect differential amplifier means having first and second branches coupled between said current source means and a power source means for passing respective portions of said constant current;

said first branch including a plurality of serially coupled enhancement field effect transistors having a positive threshold voltage and having respective gates for receiving respective input logic signals; and

said second branch including a depletion field effect transistor having a negative threshold voltage and a grounded gate, whereby the magnitudes of said current portions in said first and second branches are representative of the magnitude of said input logic signals relative to said positive threshold voltage plus the absolute value of said negative threshold voltage.