Data steering logic for the output of a cache memory having an odd/even bank structure

• US 4,445,172 A
• Filed: 12/31/1980
• Issued: 04/24/1984
• Est. Priority Date: 12/31/1980
• Status: Expired due to Fees

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Peters, Arthur, Stanley, Philip E.
• Primary Examiner(s): Atkinson, Charles E.
• Assistant Examiner(s): HARKCOM, GARY V
• Application Number:
  US06/221,853
• Time in Patent Office: 1,210 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/3
• CPC Class Codes: G06F 12/0851 Cache with interleaved addressing
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.

Claims

1. In a data processing system wherein data words are stored in a system memory including a plurality of storage locations and each of the storage locations in associated with either an odd or even address number and wherein one of a plurality of system elements requests the transfer of a pair of successively addressed data words by supplying in a memory request the address number associated with the first of the pair of data words, a cache memory comprising:

memory means for storing a subset of said data words stored in said system memory, said memory means having an odd memory module for storing data words associated with odd address numbers and an even memory module for storing data words associated with even address numbers, said memory means for selectively outputting said pair of requested data words including a first data word associated with an even address number and a second data word associated with an odd address number;

means for controlling said memory means to output said first and second data words;

means for transferring said outputted pair of data words from said cache memory to said one of said system elements; and

means for selectively supplying said outputted pair of data words to said transferring mean such that the first and second data words in said pair of data words to be simultaneously transferred by said transferring means comprise either said first and second outputted data words, respectively, or said second and first outputted data words, respectively,

wherein said odd memory moduel includes a first odd random access memory having a first odd data storing portion including a first plurality of odd addressable memory locations and a first set of odd address input terminals for receiving an address number representative of a said odd address number and for addressing one of said first odd memory locations in said first data storing portion in accordance with said address number representative of a said odd address number received by said first odd address input terminals to output said second data word from said first odd data storing portion, and

a second odd random access memory having a second odd data storing portion including a econd plurality of odd addressable memory locations and a second set of odd address input terminals for receiving said address number representative of a said odd address number to address one of said second odd memory locations in said second odd data storing portion in accordance with said address number representative of a said odd address number received by said second odd address input terminals and for outputting said second data word from said second odd data storing portion,

wherein said even memory module includes a first even random access memory having a first even data storing portion and including a first plurality of even addressable memory locations and a first set of even address input terminals for receiving an address number representative of a said even address number and for addressing one of said first even memory locations in said first even data storing portion in accordance with said address number representative of said received even address number to output said first data word from said first even data storing portion, and

a second even random access memory having a second even data storing portion including a second plurality of addressable even memory locations and a second set of even address input terminals for receiving said address number representative of a said even address number to address one of said second even memory locations in said second even data storing portion in accordance with said address number representative of a said even address number received by said second even address input terminals and for outputting said first data word from said second even data storing portion,

wherein said first data word and said second data word are outputted from said first even data storing portion and said first odd data storing portion, respectively, or from said second even data storing portion and said second odd data storing portion, respectively.

2. A cache memory according to claim 1 further including addressing means comprising a plurality of address driver circuits for supplying said address number representative of an even address number to said sets of first and second even address input terminals and said address number representative of a said odd address number to said sets of first and second odd address input terminals.

3. A cache memory according to claim 2 wherein said transferring means comprises a bus means coupling said cache memory to said one of said system elements and including a low order data word transfer means and a high order data word transfer means, said low order data word transfer means and said high order data word transfer means for transferring to said system elements said data words outputted by said first and second odd and even data storing portions.

4. A cache memory according to claim 3 wherein said supplying means comprises a level one data output multiplexer for receiving said data word outputted from said first even data storing portion and said data word outputted from said first odd data storing portion and for (1) supplying said data word received from said first even data storing portion to said low order data word transfer means and said data word received from said first odd data storing portion to said high order data word transfer means when said memory request address number is even, and (2) supplying said data word received from said first odd data storing portion to said low order data word transfer means and said data word received from said first even data storing portion to said high order data word transfer means when said supplied memory request address number is odd.

5. A cache memory according to claim 4 wherein said supplying means further comprises a level two data output multiplexer for receiving said data word outputted from said second even data storing portion and said data word outputted from said second odd data storing portion and for (1) supplying said data word received from said second even data storing portion to said low order data word transfer means and said data word received from said second odd data storing portion to said high order data word transfer means when said supplied memory request address number is even, and (2) supplying said data word received from said second odd data storing portion to said low order data word transfer means and said data word received from said second even data storing portion to said high order data word transfer means when said supplied memory request address number is odd.

6. A cache memory according to claim 5 wherein said system memory transfers data words to said cache memory for storage therein in response to requests for data words not presently stored in said odd memory module or said even memory module, said cache memory further including:

a local data input multiplexer for receiving said pair of data words transferred from said system memory and for transferring said received pair of data words to said level one data output multiplexer, said level one data output multiplexer for supplying said data word in said pair of data words associated with said memory request address number to said low order data word transfer means and an other data word of said received pair of data words to said high order data word transfer means.