Digital data processing system utilizing a unique arithmetic logic unit for handling uniquely identifiable addresses for operands and instructions

• US 4,445,177 A
• Filed: 05/22/1981
• Issued: 04/24/1984
• Est. Priority Date: 05/22/1981
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Mundie, Craig J., Bernstein, David H., Wallach, Steven J., Jones, Thomas M., Belgard, Richard A., Schleimer, Stephen I., Gavrin, Edward S., Pilat, John F., Bachman, Brett L., Bratt, Richard G., Clancy, Gerald F.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Fleming, Michael R.
• Application Number:
  US06/266,411
• Time in Patent Office: 1,068 Days
• Field of Search: 364/200, 364/900
• US Class Current: 712/245
• CPC Class Codes: G06F 8/41 Compilation

Abstract

A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described withreference to the invention herein, indentify locations of object information to be accessed by utilizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format. Arithmetic logic unit (ALU) means, also as particularly described with reference to the invention herein, include general register means having three vertically oriented parts for storing such respective fields. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

Claims

1. In a digital computer system including processor means for performing operations upon operands, memory means for storing said operands and instruction for directing said operations, selected combinations of operands and instructions being identifiable as objects for containing said selected combinations of operands and instructions, bus means for conducting operands and instructions between said memory means for conducting operands between said digital computer system and devices external to said digital computer system, said processor means comprising:

ALU means connected from said bus means for performing said operations,

addressing means connected to said bus means for providing addresses for controlling the transfer of operands and instructions between said memory means and said processor means, each one of said addresses comprising

an object field for identifying a corresponding one of said objects,

an offset field for specifying a first number of information bits of offset relative to the start of said corresponding one of said objects, and

a length field for specifying a second number of information bits of said corresponding one of said objects following said first number of information bits to be transferred between said memory means and said processor means, and

microcode control means for storing sequences of microinstructions for controlling at least said processor means, said microcode control means connected to said bus means and responsive to said instructions for providing said sequences of microinstructions to said processor means,

said ALU means including

general register file means connected from said bus means for storing said operands and said addresses,

said general register file means comprising a plurality of vertically ordered registers vertically divided into three parallel-operating and addressed parts,

a first part of said general register file means comprising first register file means for storing object fields of said addresses,

a second part of said general register file means comprising second register file means for storing offset fields of said addresses and operands, and

a third part of said general register file means comprising third register file means for storing length fields of said addresses,

address ALU means connected to said general register file means and to said bus means and responsive to said sequences of microinstructions for performing operations on said addresses, and

string transfer ALU means for providing strings of successive addresses for controlling transfer of successive segments of said operands between said memory means and said processor means,

said second number of information bits of each of said operands being greater than the width of said bus means,

each one of said strings of successive addresses corresponding to one of said operands,

each one of said successive addresses corresponding to a successive segment of said corresponding one of said operands, and

each one of said segments including a said second number of information bits equal to or less than said width of said bus means.

2. The digital computer system of claim 1, wherein

a first part of said second register file means stores offset fields of said successive addresses, and

a corresponding first part of said third register file means stores length fields of said successive addresses, and

said string transfer ALU means is connected from said second register file means and said third register file means for providing said offset and length fields of said successive addresses, and is further connected to said second register file means and said third register file means to increment and decrement said offset and length fields of said successive addresses stored in said first parts of said second register file means and said third register file means.

3. The digital computer system of claim 2, wherein said string transfer means further comprises:

bias register file means connected and operating in parallel with said third register file means for storing next length fields to said successive addresses, and

said string transfer ALU means is connected to said bias register file means for providing said next length fields.