Memory device

• US 4,445,204 A
• Filed: 10/05/1981
• Issued: 04/24/1984
• Est. Priority Date: 10/03/1980
• Status: Expired due to Term

• Current Assignee: Nippon Electric Company Limited (NEC Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Nishiguchi, Yukihiro
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US06/308,645
• Time in Patent Office: 932 Days
• Field of Search: 365/194, 365/189, 365/233
• US Class Current: 365/189.19
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A memory device provided with an improved control circuit for enabling effective interface with a CPU. The device comprises a memory circuit, a first terminal for receiving a strobe signal for placing the memory circuit in an accessed state, a second terminal for receiving a chain of clock signals, digital counter for counting the clock signals in response to the strobe signal having a plurality of different value of count, output terminals, a circuit for selectively deriving a count signal from one of the count output terminal according to a programmed state, and a ready signal generating circuit for generating a ready signal for indicating the completion of the access operation of the memory circuit in response to the count signal.

Claims

1. A memory device comprising a plurality of memory cells, means for receiving address signals, means for selecting at least one of the memory cells in accordance with said address signals, means for receiving an access request signal, at least one output terminal, means responsive to said access request signal for producing read-out signal from the selected memory cell after its operation period, means for receiving a chain of clock signals, digital delay means including a plurality of bit stages, means for applying said access request signal to said digital delay means, means for applying said clock signals to said digital delay means, said digital delay means sequentially energizing said plurality of bit stages one by one in accordance with the increase of number of said clock signals applied thereto after receipt of said access request signal, programmable means having a plurality of input lines each receiving a signal from the associated bit stage of said digital delay means, an output line intersecting with said input lines and a plurality of programmable elements disposed at the intersections of said input lines, each of said programmable elements being capable of taking one of a first state for electrically isolating said output line and the associated input line and a second state for providing an electric path between said output line and the associated input line, and means for generating a ready signal when said output line is energized after the receipt of said access request signal, whereby said ready signal is produced through a desired period defined by the bit stage of said digital delay means associated to the input line coupled to the programmable element made in said second state from the time point of the receipt of said access request signal.

2. The device according to claim 1, in which said digital delay means includes a counter made of a plurality of bit stages.

3. The device according to claim 1, in which said digital delay means include a shift register made of a plurality of bit stages.

4. The device according to claim 1, in which said desired period is selected not less than the operation period of said producing means.

5. An integrated circuit comprising a memory circuit, a first terminal for receiving an access request signal for commanding an access request to said memory circuit, a second terminal for outputting read out data from said memory circuit through a response time thereof from the receipt of said access request signal, a third terminal for receiving a chain of clock signals, a shift register having a plurality of bit stages and having a reset terminal, means for applying a reset signal to said reset terminal when said access request signal is absent thereby to place the bit stages in their initial states, means for applying an input signal to said shift register when said access request signal is present, means for applying said chain of clock signals to said shift register as shift pulses, said shift register shifting said input signal one by one to said bit stages in accordance with said clock signal when said access request signal is present, a fourth terminal, a selection circuit having a plurality of input terminals, an output terminal, and selection means responsive to a desired one of said input terminals for energizing said output terminal, means for supplying said input terminals with output signals from said bit stages, and means responsive to a signal of said output terminal for applying a ready signal for indicating that data at said second terminal becomes valid to said fourth signal.

6. The circuit according to claim 5, in which said selection means includes a plurality of programmable elements, each being programmable into either a conducting state or a nonconducting state and coupled between the associated input terminal and said output terminal.

7. An integrated circuit comprising a memory circuit, a first terminal for receiving an access request signal for designating a read operation to said memory circuit, a second terminal for outputting read out data from said memory circuit through an operation time from the receipt of said access request signal, a third terminal for receiving a clock signal, a counter having a count input terminal and a plurality of different count output terminals, means for applying said clock signal to said count input terminal of said counter, means for controlling said counter so as to start counting said clock signals in response to receipt of said access request signal, a programmable selection circuit having a plurality of input lines coupled to said count output terminals, an output line, and a plurality of program elements each coupled between the corresponding input line and said output line, an electrical coupling between a selected input line and the output line being provided by the programmed state of the program element associated to the selected input line, a fourth terminal, means responsive to a signal from said output line of said programmable selection circuit for generating a ready signal for indicating that read out data is outputted at said second terminal, and means for applying said ready signal to said fourth terminal.

8. An integrated circuit comprising a memory circuit, a first terminal for receiving a chip select signal for enabling said memory circuit, a second terminal for receiving an access request signal for commanding a read operation to said memory circuit, a third terminal for receiving a chain of clock signals, a shift register circuit having a data terminal, a shift terminal and a reset terminal and composed of plurality of bit stages, means for connecting said third terminal to said shift terminal, a NOR gate receiving said chip select signal and said access request signal at its input terminal, a first inverter circuit having an input terminal coupled to an output terminal of said NOR gate, means for connecting an output terminal of said first inverter circuit, means for connecting said data input terminal of said shift register to the output terminal of said NOR gate, a plurality of first lines each coupled to associated one of outputs of said bit stages, a second line intersecting with said first lines, a plurality of program elements disposed at said intersections of said first lines and said second line, said program elements having either of first mode responsive to a level change of the associated first line for causing a level change at said second line and second mode causing no level change at said second line irrespective of the level change of the associated first line, a second inverter circuit having an input terminal coupled to said second line, a fourth terminal, a NAND gate receiving an output signal from said second inverter circuit and the output signal from said NOR gate, and means for applying an output signal to said fourth signal.

9. An integrated circuit comprising a memory circuit, a first terminal for receiving a strobe signal for making said memory circuit in an accessed state, a second terminal for receiving a chain of pulse signals, a counter circuit having a reset terminal, a count input terminal and a plurality of count output terminals, a first inverter receiving said strobe signal and an output terminal coupled to said reset terminal, means for supplying said count input terminal with said pulse signals, a plurality of program elements each programmable to provide a first state producing a first potential or a second state producing a second different potential, a plurality of Exclusive -OR gates, each receiving a signal from the associated count output terminal and a potential from the associated program element, an AND gate receiving output signals from said Exclusive-OR gates at its input terminals, a NOR gate receiving an output signal from said AND gate and said strobe signal, a third terminal, and means for connecting an output terminal of said NOR gate to said third terminal.

10. A memory device comprising a memory circuit, first means for receiving a strobe signal for placing said memory circuit in an accessed state said memory circuit starting a memory operation in response to a receipt of said strobe signal and completing it after a predetermined time period, digital delay means composed of a plurality of delay stages each outputting a different delay time, means for applying said strobe signal to said digital delay means as an input signal to be delayed, a programmable circuit having a plurality of input lines receiving the respective outputs of said plurality of delay stages, an output line, and a plurality of programmable elements coupled to the associated input lines and to said output line, each of said programmable elements taking a first state electrically isolating the associated input line from said output line or a second state electrically coupling the associated input line to said output line, and means responsive to a signal from said output line for generating a ready signal designating operating state of said memory circuit.

11. The device according to claim 10, further comprising means for receiving a chain of clock signals, said digital delay means operable with said clock signals and responsive to said strobe signal, said digital delay means taking an initial state when said strobe signal is absent while being enabled when said strobe signal is present.

12. An integrated circuit comprising a memory circuit, first means for receiving an access request signal for requesting an access operation to said memory circuit, said memory circuit completing a memory operation after a predetermined period of time has elapsed from receipt of said access request signal, means for receiving a series of pulse signals, digital delay means operated by said pulse signals and generating a plurality of delay output signals having different values, means for starting delay operation of said digital delay means in response to the receipt of said access request signal, selection means having a plurality of programmable elements, said selection means selecting one of said delay output signals in accordance with a programmed state of said programmable elements, and means responsive to the selected delay output signal for generating a ready signal indicating the memory operation of said memory cell is completed.