MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance

• US 4,445,266 A
• Filed: 08/07/1981
• Issued: 05/01/1984
• Est. Priority Date: 08/07/1981
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: Mostek Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Mai, Chao C., Gosney, William M., Gulyas, Donald J., Whitney, William M.
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US06/290,833
• Time in Patent Office: 998 Days
• Field of Search: 29/571, 29/578, 29/591, 148/187
• US Class Current: 438/238
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: Y10S 438/907 Continuous processing

Abstract

A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors on P-type semiconductor substrate (10). A layer of oxide (14) is formed on the substrate (10) and then a polysilicon layer (16) is formed on top of the oxide layer (14). A layer of silicon nitride (18) is deposited on top of the polysilicon layer (16). The silicon nitride layer (18), polysilicon layer (16) and oxide layer (14) are selectively etched to form a conductor pattern. The conductor pattern defines a gate electrode and a plurality of interconnecting lines (42) that interconnect transistors to each other and to the peripheral circuits that drive the transistors. The source and drain regions (26 and 28) are ion implanted with arsenic ions. The exposed sidewalls of the polysilicon layer (16) are oxidized lateral and subjacent to the silicon nitride layer (18). The oxidation forms a lateral band of oxide (32) on the polysilicon layer (16) and effectively reduces the conductive width of the polysilicon layer (16). The reduced conductive width reduces the overlap capacitance. The silicon nitride layer (18) is then removed and a layer of tungsten (34) is deposited by hot-wall, low-pressure chemical vapor deposition (LPCVD). The tungsten layer (34) selectively adheres to the polysilicon layer (18) providing a low resistance path for the conductors. The tungsten layer (18) forms both a gate electrode and the low resistance interconnect lines (42) or "runs." A heat treatment may then be applied to the combined tungsten layer (34) and the polysilicon layer (16) to form a composite conductor of tungsten silicide. Thereafter the interconnect lines (42) and gate electrodes are covered by a low temperature oxide (36).

Claims

1. A method for fabricating a conducting structure for an integrated circuit comprising the steps of:

forming an insulating layer on a semiconductor substrate;

forming a polycrystalline silicon layer on said insulating layer, said layer having a propensity for oxidation;

forming an oxidation resistant layer on said polycrystalline silicon layer;

selectively etching said oxidation resistant layer, said polycrystalline silicon layer and said insulating layer in a pattern to define a plurality of conducting paths, said selective etching exposing the sidewalls of said first conducting layer;

selectively oxidizing the exposed sidewalls of said polycrystalline silicon layer, said selective oxidation perpendicular to the sidewalls of said polycrystalline silicon layer and subjacent to said oxidation resistant layer such that only a portion of said polycrystalline silicon layer is oxidized wherein the width of said polycrystalline silicon layer is reduced;

removing said oxidation resistant layer;

forming a conducting layer on said polycrystalline silicon layer, said conducting layer adhering only to the nonoxidized portion of said polycrystalline silicon layer wherein the nonoxidized portion of said polycrystalline silicon layer defines a template for a primary conductor path, said conducting layer having a higher conductivity than said polycrystalline silicon layer, wherein said conducting layer forms said primary conductor path; and

forming a protective layer over said conducting layer.

2. The method of fabricating a conducting structure as defined in claim 1 wherein the step of forming said insulating layer is comprised of the step of forming an oxide layer.

3. The method of fabricating a conducting structure as defined in claim 1 wherein the step of forming said oxidation resistant layer comprises the step of forming a silicon nitride layer.

4. The method of fabricating a conducting structure as defined in claim 1 wherein the step of forming said conducting layer comprises the step of forming a tungsten layer.

5. The method of fabricating a conducting structure as defined in claim 1 wherein the step of forming said protective layer comprises the step of growing a layer of low temperature oxide.

6. The method of fabricating a conducting structure as defined in claim 1 further comprising the step of applying a heat treatment after forming said conducting layer, said heat treatment combining said polycrystalline silicon layer and said conducting layer into a composite conducting layer.

7. The method of fabricating a conducting structure as defined in claim 1 wherein the step of removing said oxidation resistant layer comprises the step of selectively removing said oxidation resistant layer whereby a portion of said oxidation resistant layer will remain on said polycrystalline silicon layer to prevent adherance of said conducting layer to said first conducting layer over said portions thereby retaining the conductivity of polycrystalline silicon layer in said portion to form a series resistor.

8. A method for fabricating a conducting structure for an integrated circuit comprising the steps of:

forming an oxide layer on a semiconductor substrate;

forming a polycrystalline silicon layer on said oxide layer;

forming a silicon nitride layer on said polycrystalline silicon layer;

selectively etching said nitride and polycrystalline silicon layers in a pattern to define a plurality of conducting paths, said selective etching exposing the sidewalls of said polycrystalline silicon layer;

selectively oxidizing the exposed sidewalls of said polycrystalline silicon layer, said selective oxidation perpendicular to the sidewalls of said polycrystalline silicon layer and subjacent to said silicon nitride layer such that only a portion of said polycrystalline silicon layer is oxidized;

selectively removing said silicon nitride layer whereby portions of said silicon nitride layer remain on said polycrystalline silicon layer;

forming a tungsten layer on said polycrystalline silicon layer by hot wall low pressure chemical vapor deposition, said tungsten layer selectively adhering only to the exposed non-oxidized portion of said polycrystalline silicon layer wherein said non-oxidized portion of said polycrystalline silicon layer defines a primary conductor path, thereby reducing the conductive width of said polycrystalline silicon layer and said tungsten layer, wherein said tungsten layer forms said primary conductor path and said portions of said silicon nitride layer on said polycrystalline layer form a series resistor in said primary conductor path; and

forming a layer of low temperature oxide over said tungsten layer.

9. A method for fabricating a conducting structure for an integrated circuit as defined in claim 8 comprising a further step of applying a heat treatement to said polycrystalline silicon and tungsten layers prior to forming said layer of low temperature oxide thereby forming a layer of tungsten silicide.

10. A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors comprising the steps of:

forming an insulating layer on a semiconductor substrate;

forming a polycrystalline silicon layer having a propensity for oxidation;

forming an oxidation resistant layer on said polycrystalline silicon layer;

selectively etching said oxidation resistant layer, said polycrystalline silicon layer and said insulating layer in a pattern to define a plurality of channel regions for the plurality of transistors and a plurality of interconnects between said transistors and the peripheral circuits for driving said transistors wherein said selective etching also exposes the sidewalls of said polycrystalline silicon layer;

applying an ion implantation to form source and drain regions of the plurality of transistors in said silicon substrate, said source and drain regions on opposite sides of said channel regions, said oxidation resistant layer having sufficient thickness to obstruct said ion implantation in said first conducting layer;

selectively oxidizing the exposed sidewalls of said polycrystalline silicon layer, said oxidation extending perpendicular to the exposed sidewalls of said polycrystalline silicon layer and subjacent to said oxidation resistant layer such that only a portion of said polycrystalline silicon layer is oxidized wherein said oxidized portion loses its conductive properties thereby reducing the conductive surface area of said polycrystalline silicon layer structure at or near the edges of said source and drain regions resulting in reduced overlap capacitance;

removing the remaining portion of said oxidation resistant layer;

forming a conducting layer on said polycrystalline silicon layer, said second conducting layer selectively adhering to the nonoxidized portion of said polycrystalline silicon layer, said conducting layer having a higher conductivity than said polycrystalline silicon layer, said conducting layer forming both a gate electrode for each of the plurality of transistors over said channel regions and a plurality of low resistance interconnecting lines; and

forming a layer of protective insulating material on said second conducting layer.

11. The method in claim 10 wherein the step of forming said insulating layer comprises the step of growing an oxide layer.

12. The method in claim 10 wherein the step of forming said oxidation resistant layer comprises the step of depositing a silicon nitride layer.

13. The method in claim 10 wherein the step of applying said ion implantation comprises the step of applying an ion implantation of arsenic ions.

14. The method in claim 10 wherein the step of forming said second conducting layer comprises the step of depositing a tungsten layer by hot-wall low-pressure chemical vapor deposition.

15. The method of claim 10 wherein the step of forming said protective insulating layer comprises the step of depositing a low temperature oxide.

16. The method of claim 10 further comprising the step of applying a heat treatment after forming said conducting layer, said heat treatment combining said first and second conducting layers into a composite conducting layer.

17. The method of claim 16 wherein said composite conducting layer comprises tungsten silicide.

18. The method of claim 10 wherein the step of removing said oxidation resistant layer comprises the step of selectively removing said oxidation resistant layer whereby a portion of said oxidation resistant layer will remain to prevent adherance of said conducting layer to said polycrystalline silicon layer over said narrow strip thereby retaining the conductivity of said polycrystalline silicon layer in said portion to form a series resistor.

19. A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors comprising the steps of:

forming a layer of oxide on a semiconductor substrate;

forming a layer of polycrystalline silicon on said oxide layer;

forming a layer of silicon nitride on top of said polycrystalline silicon layer;

selectively etching said silicon nitride and polycrystalline silicon layers and said oxide layers in a pattern that defines a plurality of channel regions for the plurality of transistors and a plurality of interconnects between said transistors and the peripheral circuits for driving said transistors wherein said selective etching also exposes the sidewalls of said polycrystalline silicon layer;

applying an ion implantation of arsenic ions to form source and drain regions of the plurality of transistors in said semiconductor substrate, said source and drain regions on opposite sides of said channel region, said silicon nitride layer having sufficient thickness to obstruct said ion implantation in said polycrystalline silicon layer;

selectively oxidizing the exposed sidewalls of said polycrystalline silicon layer, said oxidation extending perpendicular to the exposed sidewalls of said polycrystalline silicon layer and subjacent to said silicon nitride layer such that only a portion of said polycrystalline silicon layer is oxidized thereby reducing the conductive surface area of said polycrystalline silicon layer at or near the edges of said source and drain regions resulting in reduced overlap capacitance;

selectively removing said silicon nitride layer whereby portions of said silicon nitride layer remain on said polycrystalline layer;

forming a tungsten layer by hot-wall, low-pressure chemical vapor deposition on said polycrystalline silicon layer, said tungsten layer selectively adhering to the exposed nonoxidized portion of said polycrystalline silicon layer, said tungsten layer forming a gate electrode for each of the plurality of transistors over said channel region and a plurality of low resistance interconnect lines, said portion of said polycrystalline silicon covered by said silicon nitride forming a resistor in series with said low resistance interconnect lines; and

forming a layer of protective material by depositing a low temperature oxide on said tungsten layer.

20. The method in claim 19 comprising a further step of applying a heat treatment to the combination of said polycrystalline and tungsten layers prior to forming said layer of low temperature oxide thereby forming a layer of tungsten silicide.

21. A method of fabricating a metal oxide semiconductor field effect transistor comprising the steps of:

forming an insulating layer on a semiconductor substrate;

forming a polycrystalline silicon layer on said insulating layer, said layer having a propensity for oxidation;

forming an oxidation resistant layer on said polycrystalline silicon layer;

selectively etching said oxidation resistant layer, said polycrystalline silicon layer and said insulating layer in a pattern to define a channel region of the transistor and expose the sidewalls of said first conducting layer;

applying an ion implantation to form a source and drain region of the transistor in said silicon substrate, said source and drain region on opposite sides of said channel region, said oxidation resistant layer having sufficient thickness to obstruct said ion implantation in said first conducting layer;

selectively oxidizing the exposed sidewalls of said polycrystalline silicon layer, said oxidation extending perpendicular to the exposed sidewalls of said first conducting layer and subjacent to said oxidation resistant layer such that only a portion of said polycrystalline silicon layer is oxidized whereby said oxidized portion loses its conductive properties thereby reducing the conductive surface of said first conducting layer at or near the edges of said source and drain region resulting in reduced overlap capacitance;

removing remaining portion of said oxidation resistant layer;

forming a conducting layer on said first conducting layer, said second conducting layer having a higher conductivity than said polycrystalline silicon layer, said conducting layer selectively adhering to the non-oxidized portion of said polycrystalline silicon layer wherein a gate electrode of the transistor is formed; and

forming a layer of protective insulating material on said second conducting layer.

22. The method in claim 21 wherein the step of forming said insulating layer comprises the step of growing an oxide layer.

23. The method in claim 21 wherein the step of forming said oxidation resistant layer comprises the step of depositing a silicon nitride layer.

24. The method in claim 21 wherein the step of applying said ion implantation comprises the step of applying an ion implantation of arsenic ions.

25. The method in claim 21 wherein the step of forming said conducting layer comprises the step of depositing a tungsten layer by hot wall chemical vapor deposition.

26. The method in claim 21 wherein the step of forming said protective insulating layer comprises the step of depositing a low temperature oxide.

27. The method in claim 21 further comprising the step of applying a heat treatment after forming said second conducting layer, said heat treatment combining said polycrystalline silicon layer and said conducting layer into a composite conducting layer.

28. The method in claim 27 wherein said composite conducting layer comprises tungsten silicide.

29. A method of fabricating a metal oxide semiconductor field effect transistor comprising the steps of:

forming a layer of oxide on a semiconductor substrate;

forming a layer of polycrystalline silicon on said oxide layer;

forming a layer of silicon nitride on top of said polycrystalline silicon layer;

selectively etching said silicon nitride, polycrystalline silicon and oxide layers in a pattern that defines a channel region of a transistor whereby the sidewalls of said polycrystalline layer are exposed;

applying an ion implantation of arsenic ions to form a source and drain region of the transistor in said semiconductor substrate, said source and drain regions on opposite sides of said channel region, said silicon nitride having sufficient thickness to obstruct said ion implantation in said polycrystalline silicon layer;

selectively oxidizing the exposed sidewalls of said polycrystalline silicon layer, said oxidation extending perpendicular to the exposed sidewalls of said polycrystalline silicon layer and subjacent to said silicon nitride layer such that only a portion of said polycrystalline silicon layer is oxidized thereby reducing the conductive surface area of said polycrystalline silicon layer at or near the edges of said source and drain region resulting in reduced overlap capacitance;

forming a layer of tungsten by hot-wall low-pressure chemical vapor deposition on said polycrystalline silicon layer, said tungsten layer selectively adhering to the non-oxidized portion of said polycrystalline layer wherein a gate electrode is formed; and

forming a layer of protective material by depositing a low temperature oxide on said tungsten layer.

30. The method in claim 29 further comprising the step of applying a heat treatment to the combination of said tungsten layer and said polycrystalline silicon layer to form a composite layer of tungsten silicide.