PCM Signal processing circuit

• US 4,446,490 A
• Filed: 11/17/1981
• Issued: 05/01/1984
• Est. Priority Date: 11/18/1980
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.), Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Sony Corporation (Sony Group Corp.), Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Kojima, Tadashi, Hoshimi, Susumu
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US06/322,279
• Time in Patent Office: 896 Days
• Field of Search: 360/13, 360/14.1, 360/32, 360/33
• US Class Current: 360/32
• CPC Class Codes: G11B 2220/90 Tape-like record carriers
• CPC Class Codes: G11B 27/032 on tapes G11B27/036, G11B27/038 take precedence
• CPC Class Codes: G11B 27/323 Time code signal, e.g. on a cue track as SMPTE- or EBU-time code
• CPC Class Codes: G11B 5/09 Digital recording

Abstract

A PCM signal processor having a signal input terminal which receives a PCM data signal, a memory for storing the PCM data signal, a standardized signal input terminal for providing a standardized signal corresponding to a synchronizing signal for synchronizing the PCM data signal reproducing apparatus, an address counter for designating the address of the memory which is to be read and means for providing said address counter with preset data in response to the standardized signal.

Claims

1. A PCM signal processing circuit comprising, a signal input terminal for receiving a PCM data signal from PCM data signal reproducing apparatus, a memory for storing said PCM data signal and to be designated an address thereof to be written by an address signal being produced with regard to said PCM data signal, a standardized signal input terminal for receiving a standardized signal corresponding to a synchronizing signal for synchronizing said PCM data signal reproducing apparatus, an address counter for designating an address of said memory to be read, and means for providing said address counter with preset data in response to said every standardized signal as a load signal so that said address counter begins counting read pulses synchronized with said standarized signal from said preset data.

3. A PCM processing circuit according to claim 1 wherein said synchronizing signal is generated by a recording clock signal generator and a master clock signal generator.

4. A PCM processing circuit according to claim 1 including address selectors, an adder receiving output of said address selectors and said address counter and supplying an input to said memory.

2. A PCM signal processing circuit comprising, a signal input terminal for receiving a PCM data signal, PCM data signal reproducing apparatus, a memory for storing said PCM data signal, a standarized signal input terminal for providing a standarized signal as a synchronizing signal for synchronizing said PCM data signal reproducing apparatus, an address counter for designating an address of said memory to be read, and means for providing said address counter with preset data in response to said standardized signal, phase comparing means for comparing a word clock signal which is being synchronized to said standardized signal with another word clock signal which controls said memory in phase and for generating a detecting signal when phase synchronizing of said word clock signals is obtained, and control means for controlling so that said preset data is loaded into said address counter in response to said detecting signal.

5. A PCM signal processing circuit comprising, a reproducing video recorder, a data extracting circuit and a synchronizing signal separator circuit receiving outputs of said reproducing video recorder, a recording clock signal generator supplying a sync signal to said reproducing video recorder, a word selector connected to the output of said data extracting circuit, a memory receiving the output of said word selector, a first counter, a first comparator receiving inputs from said first counter, a first switch for connecting in a first position the output of said recording clock signal generator to said first comparator, a crystal oscillator, a controllable counter receiving inputs from said first comparator, a second switch which in a first position supplies the output of said crystal oscillator to said controllable counter, said first counter connected to receive an output of said controllable counter, and a read/write controller receiving an output from first counter and supplying inputs to said memory.

6. A PCM signal processing circuit according to claim 5 including a third counter receiving the output of said first counter, a second comparator receiving inputs from said third counter and said synchronizing signal separator, and a controllable oscillator receiving the output of said second comparator and supplying an output to said controllable counter when said second switch is in a second position.

7. A PCM signal processing circuit according to claim 6 including a low pass filter connected between said controllable oscillator and said second comparator.

8. A PCM signal processing circuit according to claim 6 including a fourth counter connected between said first and third counters.

9. A PCM signal processing circuit according to claim 6 including a buffer counter receiving inputs from said read/write controller, an address counter receiving an input from said read/write controller, an address selector receiving an output from said buffer counter, and an adder receiving outputs from said address counter and said address selector and supplying an input to said memory.

10. A PCM signal processing circuit according to claim 9 wherein said address selector receives inputs from said word selector, and said first and fourth counters and supplies an input to said memory.

11. A PCM signal processing circuit according to claim 10 including a decoder connected between certain inputs of said address selector and said word selector.

12. A PCM signal processing circuit according to claim 9 including an AND gate receiving inputs from said recording clock signal generator and said first comparator, and a set pulse generator receiving the output of said AND gate and supplying an output to said buffer counter.

13. A PCM signal processing circuit according to claim 12 wherein said set pulse generator supplies inputs to said fourth counter.

14. A PCM signal according to claim 9 including an error-correction circuit which receives the output of said memory.