Buffer circuit including a current leak circuit for maintaining the charged voltages

• US 4,447,745 A
• Filed: 11/18/1981
• Issued: 05/08/1984
• Est. Priority Date: 11/19/1980
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Takemae, Yoshihiro, Kabashima, Katsuhiko, Mezawa, Tsutomu, Nozaki, Shigeki, Enomoto, Seiji
• Primary Examiner(s): Anagnos, Larry N.
• Assistant Examiner(s): Hudspeth, David R.
• Application Number:
  US06/322,719
• Time in Patent Office: 902 Days
• Field of Search: 307/481-482, 307/443, 307/491, 307/549-550, 307/577-578, 307/583-584, 307/264, 307/269, 307/591, 307/601, 307/605, 307/518
• US Class Current: 327/292
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: H03K 19/01735 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals

Abstract

A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

Claims

1. A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising:

an input stage circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node in response thereto, the node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage lower than the voltage of the inverted input clock signal;

a bootstrap circuit, operatively connected to said input stage circuit, for generating a boosted signal in response to the output signal of said input stage circuit, said bootstrap circuit including a first field effect transistor operatively connected to the node, for receiving the output signal of said input stage circuit;

an output circuit, operatively connected to said bootstrap circuit, for generating the output clock signal, said output circuit including a second field effect transistor operatively connected to said bootstrap circuit for receiving the boosted signal; and

a current leak circuit operatively connected between the node of said input stage circuit and said second power terminal, for maintaining the voltage of the node being charged during the standby period at a value corresponding to the power source voltage, by leaking excess charges at the node to lower the voltage level of the node.

5. A semiconductor circuit used as a buffer circuit as defined in claim 1, 2, 3 or 4, wherein said current leak circuit comprises field effect transistors operatively connected in series.

6. A semiconductor circuit used as a buffer circuit as defined in claim 1, 2, 3 or 4, wherein said current leak circuit comprises a field effect transistor, and a resistor operatively connected in series with said field effect transistor.

7. A semiconductor circuit used as a buffer circuit as defined in claim 1, 2, 3 or 4, wherein said current leak circuit comprises a field effect transistor.

8. A semiconductor circuit used as a buffer circuit as defined in claim 1, 2, 3 or 4, wherein said current leak circuit comprises a resistor.

2. A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising:

an input stage delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node in response thereto, the node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage lower than the voltage of the inverted input clock signal;

a bootstrap circuit, operatively connected to said input stage delay circuit, for responding to the voltage of the node after the standby period by outputting a boosted signal;

an output circuit, operatively connected to said bootstrap circuit, for receiving the boosted signal of said bootstrap circuit and for generating the output clock signal; and

a current leak circuit, operatively connected between said input stage delay circuit and said second power terminal, for maintaining the voltage of the node being charged during the standby period at a value corresponding to the power source voltage by leaking excess charges at the node to lower the voltage level of the node.

3. A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising:

an input stage circuit including an input delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node, the node being charged and maintained at the power source voltage during the standby period in which the input clock signal has a voltage level lower than the voltage level of the inverted input clock signal;

a bootstrap circuit, operatively connected to said input delay circuit, for responding to the voltage of the node by generating a boosted signal in response to the output signal of said input delay circuit, said bootstrap circuit including at least a first stage transistor and a second stage transistor operatively connected to said first stage transistor at a second node;

an output circuit, operativley connected to said bootstrap circuit, for receiving the boosted signal and for generating the output clock signal; and

a current leak circuit, operatively connected between said second node and said second power terminal, for maintaining the voltage of said second node being charged during the standby period at a value corresponding to the power source voltage, by leaking excess charges at the node to lower the voltage level of the node.

4. A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising:

an input stage circuit including an input delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a first node in response thereto, the first node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage level lower than a voltage level of the inverted input clock signal;

a bootstrap circuit, operatively connected to said input delay circuit, for generating a boosted signal in response to the output signal of said input delay circuit, said bootstrap circuit including a first stage having at least a first transistor and a second transistor operatively connected to said first transistor at a second node, and a second stage having a third transistor operatively connected to said first and second transistors at the second node;

an output circuit, operatively connected to said bootstrap circuit, for receiving the boosted signal and for generating the output clock signal; and

first and second current leak circuits, said first current leak circuit operatively connected to the second node between said first and second transistors in said first stage and said second power terminal, said second current leak circuit operatively connected between the first node of said input delay circuit and said second power terminal, the voltages of the first and second nodes being maintained at a value corresponding to the power source voltage by leaking excess charges at the first and second nodes to lower the voltage level of the first and second nodes.