Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems
First Claim
1. In a data processing system which includes first and second processors (70 and 31), a memory (80) to which information can be written by each of said processors and from which information can be read by each of said processors, such memory having a plurality of locations for storing said information, and bus means (60) for interconnecting the first and second processors and said memory, to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by the other of said processors to selectively prevent the other of said processors from accessing said memory locations, the improvement comprising:
- communications control means for controlling communications between said processors and permitting the first processor to send a plurality of commands in sequence to the second processor via the bus means, and for permitting the second processor to send responses to those commands to the first processor via the bus means;
the communications control means including a plurality of locations in said memory, termed interface memory locations, adapted to serve as a communications interface between the first and second processors, all commands and responses being transmitted through such interface memory locations;
the interface memory locations comprising a pair of ring buffers;
a first one of said ring buffers being adapted to buffer the transmission of messages issued by the first processor and a second one of said ring buffers being adapted to buffer the reception of messages transmitted by the second processor;
each of said ring buffers including a plurality of memory locations adapted to receive from an associated one of said processors a descriptor signifying another location in said memory;
for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor;
for said second ring buffer, the location signified by such descriptor being a location for holding a message from the second processor; and
the communications control means permitting each of said processors to operate at its own rate, independent of the other of said processors, and to access a ring buffer for writing thereto only when the buffer does not contain information previously written to such buffer but not yet read from it and for reading to such buffer only when the buffer contains information written to it but not yet read therefrom, thus preventing race conditions from developing across said bus means in relation to accessing the interface memory locations.
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Reexamination
Accused Products
Abstract
An interface mechanism (10) between two processors, such as a host processor (70) and a processor (31) in an intelligent controller (30) for mass storage devices (40), and utilizing a set of data structures employing a dedicated communications region (80A) in host memory (80). Interprocessor commands and responses are communicated as packets over an I/O bus (60) of the host (70), to and from the communication region (80A), through a pair of ring-type queues (80D) and (80E). The entry of each ring location (e.g., 132, 134, 136, 138) points to another location in the communications region where a command or response is placed. The filling and emptying of ring entries (132-138) is controlled through the use of an `ownership` byte or bit (278) associated with each entry. The ownership bit (278) is placed in a first state when the message source (70 or 31) has filled the entry and in a second state when the entry has been emptied. Each processor keeps track of the rings'"'"' status, to prevent the sending of more messages than the rings can hold. These rings permit each processor to operate at its own speed, without creating race conditions and obviate the need for hardware interlock capability on the I/O bus (60).
275 Citations
21 Claims
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1. In a data processing system which includes first and second processors (70 and 31), a memory (80) to which information can be written by each of said processors and from which information can be read by each of said processors, such memory having a plurality of locations for storing said information, and bus means (60) for interconnecting the first and second processors and said memory, to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by the other of said processors to selectively prevent the other of said processors from accessing said memory locations, the improvement comprising:
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communications control means for controlling communications between said processors and permitting the first processor to send a plurality of commands in sequence to the second processor via the bus means, and for permitting the second processor to send responses to those commands to the first processor via the bus means; the communications control means including a plurality of locations in said memory, termed interface memory locations, adapted to serve as a communications interface between the first and second processors, all commands and responses being transmitted through such interface memory locations; the interface memory locations comprising a pair of ring buffers; a first one of said ring buffers being adapted to buffer the transmission of messages issued by the first processor and a second one of said ring buffers being adapted to buffer the reception of messages transmitted by the second processor; each of said ring buffers including a plurality of memory locations adapted to receive from an associated one of said processors a descriptor signifying another location in said memory; for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor; for said second ring buffer, the location signified by such descriptor being a location for holding a message from the second processor; and the communications control means permitting each of said processors to operate at its own rate, independent of the other of said processors, and to access a ring buffer for writing thereto only when the buffer does not contain information previously written to such buffer but not yet read from it and for reading to such buffer only when the buffer contains information written to it but not yet read therefrom, thus preventing race conditions from developing across said bus means in relation to accessing the interface memory locations. - View Dependent Claims (2, 3)
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4. In a data processing system which includes first and second processors (70 and 31), a memory (80) adapted to be used by said processors for containing information to be shared by the processors, and bus means (60) for interconnecting the first and second processors and the memory, the bus means (60) being of the type which has no hardware interlock capability which is usable by each of said processors to selectively prevent the other of said processors from accessing at least a portion of said memory, the improvement comprising:
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the first and second processors (70 and
31) being adapted to employ a portion (80A) of said memory as a communications region accessible by both of said processors, so that all commands and responses can be transmitted from one of said processors to the other of said processors through such portion of memory;the communications region of memory including a pair of ring buffers (80D and 80E); a first one of said ring buffers (80D) buffering the transmission of messages issued by the first processor (70) and a second one of said ring buffers (80E) buffering the reception of messages transmitted by the second processor (31); each of said ring buffers including a plurality of memory locations (e.g., 132, 134, 136 and
138) adapted to receive from the associated transmitting one of said processors a descriptor signifying another location in said memory;for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor; for said second ring buffer, the location signified by such descriptor being a location for storing, at least temporarily, a message from the second processor; and the first and second processors (70 and
31) further being adapted to control access to said communications region (80A) such that information written therein by one of said processors may not be read twice by the other processor and a location where information is to be written by one of the processors may not be read by the other processor before said information has been written,so that race conditions are prevented from developing across said bus means in the course of inter-processor communications, and messages are transmitted from said ring buffers in the same sequence as that in which they are issued by the processors, while each of the processors is permitted to operate at its own rate, with substantial independence from the other processor. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12)
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13. In a data processing system which includes first and second processors, (70 and 31) a memory (80) adapted to be used by said processors, and bus means (60, 110, 90) for interconnecting the first and second processors and memory to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by each of said processors to selectively prevent the other of said processors from accessing at least a portion of said memory, the improvement comprising:
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at least a portion (80A) of said memory (80) being adapted to serve as a communications region accessible by both of said processors all commands and responses being transmitted from one processor to the other through such portion of memory; means (278) for controlling access to information in said communications region whereby information written therein by one of said processors may not be read twice by the other processor and wherein a location where information is to be written by one of the processors may not be read by the other processor before said information has been written; the communications region of memory including a pair of ring buffers (80D, 80E); a first one of said ring buffers (80D) being adapted to buffer the transmission of messages issued by the first processor and a second one of said ring buffers (80E) being adapted to buffer the reception of messages transmitted by the second processor; each of said ring buffers including a plurality of memory locations (e.g., FIG. 3B-132, 134, 136,
138) adapted to receive from an associated one of said processors a descriptor (260,
264) signifying another location in said memory;for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor; and for said second ring buffer, the location signified by such descriptor being a location for holding a message from the second processor, so that race conditions are prevented from developing across said bus means and messages are transmitted from said ring buffers in the same sequence as that in which they are issued by the processors, while each of the processors is permitted to operate at its own rate, independent of the other processor. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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Specification