Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories

• US 4,450,519 A
• Filed: 11/24/1980
• Issued: 05/22/1984
• Est. Priority Date: 11/24/1980
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Laws, Gerald E., Guttag, Karl M.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): WILLIAMS JR, ARCHIE E
• Application Number:
  US06/210,106
• Time in Patent Office: 1,275 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/33
• CPC Class Codes: G06F 15/7839 with memory
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G11C 17/12 using field-effect devices

Abstract

A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort.

Claims

1. A microprocessor system including a single-chip microprocessor device (1) comprising:

(a) a memory (2) containing a plurality of locations defined by a given set of addresses and containing program instructions and data, the program instructions being of a first type and a second type, said memory being external to said device,

(b) input/output means (3,7) external to said device for receiving and transmitting information,

(c) conductor means (4,5,6,8,9) external to said device and coupled to said memory, input/output means and said device,

(d) said microprocessor device including a central processing unit connected to said memory and said input/output means by said conductor means to couple addresses, program instruction, data and information between the memory, input/output means and central processing unit, said central processing unit comprising;

an arithmetic logic unit (10) for performing arithmetic and logic operations on data,

a plurality address/data registers for containing address and data,

an instruction register (IR) for receiving a predetermined sequence of said program instructions from said memory (2) for execution by the central processing unit, such sequence of program instructions being of a predetermined instruction set,

control means (15) including decoder means responsive to program instructions of said first type in said instruction register to produce a plurality of controls (11) for defining the operation of said arithmetic logic unit and said address/data registers of the central processing unit, and responsive to program instructions of said second type to generate auxiliary controls,

(e) an auxiliary storage unit (25A, 25B) containing a plurality of locations defined by a second set of addresses which partially overlaps said given set of addresses, with means (25G, 25D, 25F) initiated by said auxiliary controls from the control means and thereby responsive to a program instruction of said second type for transferring a different sequence of program instructions from such auxiliary storage unit to said instruction register, such different sequence being composed of said program instructions of said first type.

2. A system according to claim 1 wherein said auxiliary storage unit is part of said microprocessor device on a single semiconductor integrated circuit with said central processing unit.

3. A system according to claim 2 wherein said memory is not on said integrated circuit.

4. A system according to claim 2 wherein said auxilliary storage unit and said memory are activated for memory fetch in the alternative.

5. A system according to claim 4 wherein said given set of addresses defines a memory map limited by the logic address space allowed by the number of bits of addresses coupled by said conductor means.

9. Apparatus according to claim 4 wherein said auxilliary storage unit includes both ROM and RAM.

6. A microprocessor system comprising:

a main memory (2) containing a plurality of locations defined by an address range,

a central processing unit in a semiconductor unit (1) separate from said main memory (2), said central processing unit including an arithmetic logic unit (10), a plurality of address/data registers, an instruction register (IR) for receiving program instructions for execution by the central processing unit, such program instructions being of a first type and a second type, and control means (15) responsive to a program instruction of said first type in said instruction register to produce a plurality of controls (11) for defining the operation of the arithmetic logic unit and address/data registers in the central processing unit and responsive to a program instruction of said second type in said instruction register to produce an auxiliary control,

an auxiliary storage unit (25A, 25B) containing a plurality of locations defined by a set of addresses within said address range, wherein said set may overlap addresses of said plurality of locations of said main memory,

and means (25G,25D,25F) initiated by said auxiliary control from the control means for transferring sequences of program instructions of said first type from such auxiliary storage unit to said instruction register.

7. Apparatus according to claim 6 wherein said auxilliary storage unit is on a single semiconductor integrated circuit with said central processing unit.

8. Apparatus according to claim 7 wherein said main memory is not on said integrated circuit.

10. Apparatus according to claim 8 wherein said main memory and said auxilliary storage unit are activated in the alternative.

11. Apparatus according to claim 8 wherein said address space is the logical address space allowed by the number of bits of addresses of said instructions.

12. A microprocessor system, comprising:

(a) a single-chip microprocessor device having;

(i) an arithmetic logic unit for performing arithmetic and logic operations on data applied to inputs thereof to produce a result at an output thereof,

(ii) a plurality of registers including at least one address register containing a given number of bits to provide a first set of addresses within an address range,

(iii) an instruction register for receiving program instructions for execution by the microprocessor device, such program instructions being of a first type and a second type,

(iv) control means coupled to said instruction register and responsive to a program instruction of said first type to produce a plurality of controls for defining operation of the arithmetic logic unit and plurality of registers of the microprocessor device and responsive to a program instruction of said second type to produce an auxiliary control,

(v) terminals for the device for connection to parts of said system external to said microprocessor device for coupling addresses and data,

(vi) internal bus means for intercoupling said inputs and output of the arithmetic logic unit, said plurality of registers, said instruction registers, and said terminals,

(vi) control paths connecting said plurality of controls from said control means to said arithmetic logic unit, said plurality of registers, said instruction register, said terminals, and said internal bus means,

(viii) an auxiliary storage unit containing a plurality of storage locations accessed by a second set of addresses within said address range, said auxiliary storage unit storing program instructions of said first type,

(ix) auxiliary addressing means responsive to said auxiliary control from said control means for accessing said auxiliary storage unit using said address register only in response to initiation by a program instruction in said instruction register of said second type to thereby cause execution of program instructions of said first type from said auxiliary storage unit by loading such instructions into said instruction register,

(b) a memory containing a plurality of locations defined by addresses within said address range and containing program instructions of both first and second type and data, said memory having an address input and a data output,

(c) external bus means coupling said terminals of said microprocessor device to said address input and data output of said memory.

13. A microprocessor system according to claim 12 wherein said auxiliary storage unit also contains read/write memory means for storing data.

14. A microprocessor system according to claim 13 wherein said plurality of storage locations of said auxiliary storage unit are read-only memory.

15. A microprocessor system according to claim 12 wherein memory is not accessed at the same time as said auxiliary storage unit is accessed.

16. A microprocessor system according to claim 15 wherein said auxiliary storage unit is not accessed when a program instruction of said first type is in said instruction register for execution.