Bit data operated squelch

• US 4,450,573 A
• Filed: 12/07/1981
• Issued: 05/22/1984
• Est. Priority Date: 12/07/1981
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Noble, Scott W.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/328,359
• Time in Patent Office: 897 Days
• Field of Search: 375/5, 375/94, 375/95, 375/104, 455/218, 455/219, 455/220, 455/221, 455/222, 329/104, 329/107
• US Class Current: 375/351
• CPC Class Codes: H03G 3/34 Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence

Abstract

A unique bit data operated squelch for use with a demodulator detector for phase shift keyed digital signals. The squelch detects transitions by testing a register of baseband demodulated sample synchronized to the data bit edges. The inventive data operated squelch provides bit detection with programmable parameters and is particularly suitable for implementation utilizing a microprocessor.

Claims

1. A digital bit data operated squelch circuit for a demodulator detector which provides demodulated baseband samples of bits of a digital signal synchronized with the bit edge, and clock pulses synchronized to the bit edge, said data operated squelch circuit comprising:

synchronization register means for storing the synchronized demodulated baseband samples, including at least one sample from the adjacent bit in response to a clock pulse;

logic means, coupled to the synchronization register, for generating a transition signal in response to a difference between the edge bit sample and the adjacent bit sample, and for generating a control signal in response to non-equality of at least two additional non-edge samples;

counter means, coupled to the logic means, for accumulating a count by incrementing in response to a clock pulse when the transition signal occurs, and decrementing in response to a clock pulse when a control signal occurs; and

first comparator means, coupled to the counter means, for generating a bit squelch signal in response to the counts exceeding a first predetermined threshold.

2. The digital bit data operated squelch circuit of claim 1, wherein the counter means decrements by two, and increments by one.

3. The digital bit data operated squelch circuit of claim 1, further comprising:

second comparator means, coupled to the counter means, for resetting the counter means to zero in response to the count decreasing to less than zero.

4. The digital bit data operated squelch circuit of claim 3, further comprising:

third comparator means, coupled to the counter means for loading a predetermined maximum value into the counter means in response to the count exceeding the predetermined maximum value.

5. The digital bit data operated squelch circuit of claim 4, further comprising:

hysteresis means, coupled to the counter means, for modifying the first predetermined threshold to a lower second predetermined threshold in response to the count reaching the first predetermined threshold and for resetting the threshold to the first predetermined threshold in response to the count falling below the second predetermined threshold.

6. The digital bit data operated squelch circuit of claims 1, 4 or 5, wherein the logic means, further comprises means to increment the counter means in response to the equality of at least two non-edge samples.

7. A method for bit lock detection in a communication system utilizing a demodulator detector providing demodulated baseband samples of bits of a digital signal, synchronized with the bit edge, and clock pulses synchronized to the bit edge, the method comprising the steps of:

storing the synchronized demodulated baseband samples including at least one sample from the adjacent bit, in response to a clock pulse;

generating a transition signal in response to a difference between the bit edge sample and the adjacent bit sample;

generating a control signal in response to the non-equality of at least two additional non-edge samples;

incrementing a counter in response to the transition signal and the clock pulse;

decrementing the counter in response to the control signal and the clock pulse;

generating a bit lock signal in response to the counter contents exceeding a first predetermined threshold.

8. The method of claim 7, further comprising the steps of resetting the counter to zero in response to the contents of the counter decreasing to less than zero;

loading a predetermined maximum value into the counter in response to the contents of the counter exceeding the predetermined maxmium value.

9. The method of claim 7 or 8, further comprising the steps of:

modifying the first predetermined threshold to a lower second predetermined threshold in response to the contents of the counter reaching the first predetermined threshold;

resetting the threshold to the first predetermined threshold in response to the counter contents falling below the second predetermined threshold.

10. The method of claim 7 or 8 further comprising the step of:

incrementing the contents of the counter in response to the equality of at least two non-edge samples and the clock pulse.