Bit data operated squelch
First Claim
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1. A digital bit data operated squelch circuit for a demodulator detector which provides demodulated baseband samples of bits of a digital signal synchronized with the bit edge, and clock pulses synchronized to the bit edge, said data operated squelch circuit comprising:
- synchronization register means for storing the synchronized demodulated baseband samples, including at least one sample from the adjacent bit in response to a clock pulse;
logic means, coupled to the synchronization register, for generating a transition signal in response to a difference between the edge bit sample and the adjacent bit sample, and for generating a control signal in response to non-equality of at least two additional non-edge samples;
counter means, coupled to the logic means, for accumulating a count by incrementing in response to a clock pulse when the transition signal occurs, and decrementing in response to a clock pulse when a control signal occurs; and
first comparator means, coupled to the counter means, for generating a bit squelch signal in response to the counts exceeding a first predetermined threshold.
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Abstract
A unique bit data operated squelch for use with a demodulator detector for phase shift keyed digital signals. The squelch detects transitions by testing a register of baseband demodulated sample synchronized to the data bit edges. The inventive data operated squelch provides bit detection with programmable parameters and is particularly suitable for implementation utilizing a microprocessor.
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Citations
10 Claims
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1. A digital bit data operated squelch circuit for a demodulator detector which provides demodulated baseband samples of bits of a digital signal synchronized with the bit edge, and clock pulses synchronized to the bit edge, said data operated squelch circuit comprising:
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synchronization register means for storing the synchronized demodulated baseband samples, including at least one sample from the adjacent bit in response to a clock pulse; logic means, coupled to the synchronization register, for generating a transition signal in response to a difference between the edge bit sample and the adjacent bit sample, and for generating a control signal in response to non-equality of at least two additional non-edge samples; counter means, coupled to the logic means, for accumulating a count by incrementing in response to a clock pulse when the transition signal occurs, and decrementing in response to a clock pulse when a control signal occurs; and first comparator means, coupled to the counter means, for generating a bit squelch signal in response to the counts exceeding a first predetermined threshold. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for bit lock detection in a communication system utilizing a demodulator detector providing demodulated baseband samples of bits of a digital signal, synchronized with the bit edge, and clock pulses synchronized to the bit edge, the method comprising the steps of:
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storing the synchronized demodulated baseband samples including at least one sample from the adjacent bit, in response to a clock pulse; generating a transition signal in response to a difference between the bit edge sample and the adjacent bit sample; generating a control signal in response to the non-equality of at least two additional non-edge samples; incrementing a counter in response to the transition signal and the clock pulse; decrementing the counter in response to the control signal and the clock pulse; generating a bit lock signal in response to the counter contents exceeding a first predetermined threshold. - View Dependent Claims (8, 9, 10)
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Specification