Power supply control for integrated circuit

• US 4,451,742 A
• Filed: 12/09/1983
• Issued: 05/29/1984
• Est. Priority Date: 05/27/1981
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: Mostek Corporation (Rtx Corporation)
• Inventors: Aswell, Cecil J.
• Primary Examiner(s): Goldberg, E. A.
• Assistant Examiner(s): DEBOER, TODD
• Application Number:
  US06/560,253
• Time in Patent Office: 172 Days
• Field of Search: 307/65, 307/66, 365/201, 365/229, 371/66
• US Class Current: 307/66
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: Y10S 331/03 Logic gate active element oscillator

Abstract

A power supply control circuit (20) selectively provides power to an integrated circuit from either a primary power supply terminal (22), or through terminals (24, 26) connected to backup batteries. The voltage level of the primary power is monitored continuously and when it drops to a predetermined level one of the two backup batteries is substituted to power the integrated circuit in a power-down mode. The circuit (20) includes a level detector circuit (32) and a voltage reference circuit (98). In the power-down mode one battery is connected to power the integrated circuit and this battery is continuously monitored. When the voltage of the on-line battery drops to below a fixed level in comparison to off-line battery a control logic circuit (92) activates switches (56) to substitute the off-line battery for the on-line battery. Control logic circuitry (92) is provided to disconnect the control signals from the integrated circuit to prevent loss of stored information. Further the failure of one of the backup batteries is indicated by disabling a write enable signal.

Claims

1. A method for providing power to an integrated circuit from one of a plurality of sources, comprising the steps of:

providing a primary power source and first and second backup power sources;

comparing the voltages of said first and said second backup power sources to select the backup power source having the higher voltage;

connecting the one of said backup power sources having the higher voltage to supply power to said integrated circuit when the voltage of said primary power source is less than a first predetermined voltage; and

disabling input signals to said integrated circuit when the voltage of the power source connected thereto is less than a second predetermined voltage.

2. The method recited in claim 1 including the step of disabling input signals to said integrated circuit when the voltage of the power source connected thereto is less than a predetermined voltage.

3. The method recited in claim 1 including the steps of:

monitoring the voltages of said batteries, and

disabling a write enable input signal to said memory when said memory is powered by said primary power source and the voltage of one of said batteries is less than a third predetermined voltage, the disabling of said write enable input signal preventing the writing of data in said memory and serving as a battery failure warning.

4. The method recited in claim 3 wherein said first predetermined voltage is selected to be less than said second predetermined voltage and also is selected to be greater than said third predetermined voltage.

5. A method for providing power to an integrated circuit memory which receives a write enable signal to permit writing of data states in said memory and receives a chip select signal to permit reading of data states in said memory, comprising the steps of:

providing a primary power source and at least one backup power source;

connecting said primary power source to power said memory when the voltage of said primary power source exceeds essentially the voltage of said backup power source;

connecting said backup power source to power said memory when the voltage of said primary power source is less than a first preselected voltage;

disabling said write enable signal provided to said memory when said primary power source is connected to power said memory and the voltage of said backup power source is less than a second preselected voltage; and

disabling said write enable signal and said chip select signal provided to said memory when the voltage of said primary power source is less than a third preselected voltage.

6. A power control circuit for connecting one of a plurality of power sources to an integrated circuit, comprising;

a first power terminal for receiving a primary power source;

a second power terminal for receiving a first backup power source;

a third power terminal for receiving a second backup power source;

means for comparing the voltages of said second and said third power terminals and connecting the power terminal having the higher voltage to a power terminal of said integrated circuit when the voltage at said first power terminal is less than a first predetermined voltage; and

means for connecting said first power terminal to said integrated circuit power terminal when the voltage at said first power terminal exceeds by a preset threshold the voltage at said integrated circuit power terminal;

means for comparing the voltage at said first power terminal to a second predetermined voltage for producing a control signal; and

means responsive to said control signal for disabling the input command signals to said integrated circuit when the voltage at said first power terminal is less than said second predetermined voltage.

7. The power control circuit recited in claim 6 wherein said first predetermined voltage is less than said second predetermined voltage.

8. A power control circuit for connecting one of a plurality of power sources to an integrated circuit memory which receives a write enable signal to permit writing of data states in said memory and receives a chip enable signal to permit reading and writing of data states in said memory, comprising:

a first power terminal for receiving a primary power source;

a second power terminal for receiving a first backup power source;

a third power terminal for receiving a second backup power source;

means for comparing the voltages at said second and said third power terminals to select the one of the two terminals having the higher voltage and for connecting the higher voltage terminal supply to said memory when the voltage at said first power terminal is below a first preselected voltage;

means for connecting said first power terminal to said memory when the voltage at said first power terminal exceeds by a preset threshold the voltage of the higher voltage terminal of said second and third terminals;

means connected to said second and said third power terminals for disabling said write enable signal provided to said memory when the voltage at said second or said third power terminal is less than a second preselected voltage and;

means connected to said first power terminal for disabling said write enable and said chip select signals provided to said memory when the voltage at said first power terminal is less than a third preselected voltage.

9. The power control circuit recited in claim 8 wherein said first preselected voltage is less than said second predetermined voltage and also is greater than said third predetermined voltage.

10. A power control circuit for connecting one of a plurality of power sources to an integrated circuit which receives a write enable signal to permit writing of data states in said memory and receives a chip enable signal to permit reading of data states in said memory comprising circuit elements fabricated integrally with said memory, said power control circuit comprising:

a first power terminal for receiving a primary power source;

a second power terminal for receiving a first backup power source;

a third power terminal for receiving a second backup power source;

means for comparing the voltage at said first power terminal to the voltages at said second and said third power terminals for connecting said first power terminal to said memory when the voltage at said first power terminal exceeds the voltages at said first or second power terminals;

means for comparing the voltages at said second and said third power terminals for selecting one of the terminals having the higher voltage and connecting the higher voltage terminal to said memory when the voltage at said first power terminal is less than that of said higher voltage terminal;

a voltage divider network connected between said first power terminal and ground and having a reference node;

a band gap reference circuit for comparing a reference voltage with the input thereto;

means for periodically connecting the input of said band gap reference circuit to the junction node of said voltage divider network, said second power terminal and said third power terminal;

means connected to said band gap reference circuit for disabling said write enable and said chip enable signals provided to said memory when the voltage at said first power terminal is less than a predetermined voltage; and

means connected to said band gap reference circuit for disabling said write enable signal when the voltage at said first power terminal is greater than said reference voltage and the voltage at either said second or said third power terminals in less than a preselected voltage that indicates a defective backup power source, the disabling of said write enable signal indicating that one of said backup power sources is defective.

11. A method of operation for an integrated circuit which is powered by either a primary power source or a backup power source, wherein operation of the integrated circuit is directed by at least one control signal input thereto, comprising the steps of:

connecting said primary power source to power said integrated circuit when the voltage of said primary power source exceeds a first predetermined voltage,

connecting said backup power source to power said integrated circuit when the voltage of said primary power source is less than said first predetermined voltage, and

disabling said control signal to at least partially suspend operation of said integrated circuit when the voltage of said primary power source is less than a second predetermined voltage different from said first predetermined voltage.

12. A method of operation for an integrated circuit, which is powered by either a primary power source or a backup power source, wherein the operation of the integrated circuit is directed by at least one control signal input thereto, comprising the steps of:

monitoring the voltage of said backup power source, while said integrated circuit is powered by said primary power source, for detecting a failure of said backup power source when the voltage of said backup power source becomes less than a predetermined voltage, and

disabling said control signal upon detection of the failure of said backup power source for at least partially suspending the operation of said integrated circuit while said integrated circuit is powered by said primary power source.

13. A method as recited in claim 12 wherein said step of monitoring comprises periodically comparing the voltage of said backup power supply to a reference voltage which serves as said predetermined voltage.

14. A method as recited in claim 12 wherein said step of disabling said control signal comprises inputting said control signal and a disable signal to a NAND gate which produces a selectively disabled control signal.

15. A method of operation for an integrated circuit memory which is powered by either a primary power source or a backup battery, wherein the write function of the memory is controlled by a write enable signal input thereto, comprising the steps of:

monitoring the voltage of said battery, while said memory is powered by said primary power source, for detecting a failure of said battery when the voltage of said battery becomes less than a predetermined voltage, and

disabling said write enable signal upon detection of the failure of said battery for suspending the writing of the data into said memory while said memory is owered by said primary power source.