Bus interface unit

• US 4,453,229 A
• Filed: 03/11/1982
• Issued: 06/05/1984
• Est. Priority Date: 03/11/1982
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Corporation
• Original Assignee: Grumman Aerospace Corporation (Northrop Grumman Corporation)
• Inventors: Schaire, Scott H.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/356,949
• Time in Patent Office: 817 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/109
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4213 with asynchronous protocol
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 2012/4028 the transportation system being an aircraft

Abstract

A bus interface unit for use with a multiplexed biphase serial bus includes a Mealy modeled sequence logic unit which allows flexibility in the design and implementation of a desired data transfer algorithm. The unit'"'"'s internal architecture is such that the device may be implemented on a single semiconductor chip.

Claims

1. In a multiplex data bus interface unit having a Manchester encoder/decoder providing an interface for transmit and receive shift registers to a biphase serial bus, buffer registers providing an interface for the shift registers with an internal parallel bus communicating with a parallel direct memory access data port through a bidirectional buffer, and at least one additional register responsive to the internal bus, the inmprovement comprising:

means for defining a functional state of the bus interface unit;

means for monitoring a plurality of logical signals characterizing the operational status of the bus interface unit, the monitoring means generating a plurality of control signals regulating a data transfer process between the biphase serial bus and the parallel direct memory access data port.

2. The bus interface unit of claim 1 in which the means for defining a functional state generates a plurality of state variable signals.

3. The bus interface unit of claim 2 in which the monitoring means further monitors the state variable signals.

4. The bus interface unit of claim 3 in which the means for defining a functional state is responsive to a least one of the control signals, whereby the functional state of the bus interface unit may be changed.

5. The bus interface unit of claim 4 in which the buffer providing an interface for the receive shift register to the internal parallel bus has an enable receive buffer input for controlling data flow therefrom to the internal parallel bus, said enable receive buffer input being responsive to another one of the control signals.

6. The bus interface unit of claim 5 in which the buffer providing an interface for the transmit shift register to the internal parallel bus has a load transmit buffer input for controlling data flow thereto from the internal parallel bus, said enable receive buffer input being responsive to still another one of the control signals.

7. The bus interface unit of claim 6 in which the additional register has a load input for controlling data flow thereto from the internal parallel bus, said load input to the additional register being responsive to still another one of the control signals.

8. The bus interface unit of claim 7 in which the Manchester encoder/decoder has a transmit enable input for controlling data flow from the transmit shift register to the biphase serial bus, said transmit enable input being responsive to still another one of the control signals.

9. The bus interface unit of claim 8 in which the additional register has an enable input for controlling data flow therefrom to the internal parallel bus, said enable input to the additional register being responsive to still another one of the control signals.

10. The bus interface unit of claim 8 in which the bidirectional buffer has a direction input for controlling a direction of data flow between the internal parallel bus and the parallel direct memory access data port, said direction input being responsive to still another one of the control signals.

11. The bus interface unit of claim 10 in which bidirectional buffer further has an enable buffer input for controlling data flow therethrough, said enable buffer input being responsive to still another one of the control signals.

12. The bus interface unit of claim 11 in which the additional register has an enable input for controlling data flow therefrom to the internal parallel bus, said enable input to the additional register being responsive to still another one of the control signals.

13. A bus interface unit comprising:

a receive shift register for receiving an incoming data stream from a biphase serial bus;

a transmit shift register for transmitting an outgoing data stream to the biphase serial bus;

a Manchester encoder/decoder for providing an interface for the transmit and receive shift registers to the biphase serial bus;

an internal parallel bus;

a receive buffer for providing an interface for the receive shift register to the internal parallel bus;

a transmit buffer for providing an interface for the transmit shift register to the internal parallel bus;

means for defining a functional state of the bus interface unit; and

means for monitoring a plurality of logical signals characterizing the operational status of the bus interface unit, the monitoring means generating a plurality of control signals regulating a data transfer process between the biphase serial bus and the internal parallel bus.

14. The bus interface unit of claim 13 in which the means for defining a functional state is responsive to at least one of the control signals, whereby the functional state of the bus interface unit may be changed.

15. The bus interface unit of claim 13 in which the means for defining a functional state generates a plurality of state variable signals.

16. The bus interface unit of claim 15 in which the monitoring means further monitors the state variable signals.

17. The bus interface unit of claim 16 in which the means for defining a functional state is responsive to at least one of the control signals, whereby the functional state of the bus interface unit may be changed.

18. The bus interface unit of claim 17 in which another one of the control signals controls data flow from the receive buffer to the internal parallel bus.

19. The bus interface unit of claim 18 in which still another one of the control signals controls data flow from the internal parallel bus to the transmit buffer.

20. The bus interface unit of claim 19 in which still another one of the control signals controls data flow from the transmit shift register through the Manchester encoder/decoder to the biphase serial bus.

21. The bus interface unit of claim 13 which further comprises a bidirectional buffer through which the internal parallel bus communicates with a parallel direct memory access data port.

22. The bus interface unit of claim 21 in which the means for defining a functional state generates a plurality of state variable signals.

23. The bus interface unit of claim 22 in which the monitoring means further monitors the state variable signals.

24. The bus interface unit of claim 23 in which the means for defining a functional state is responsive to at least one of the control signals, whereby the functional state of the bus interface unit may be changed.

25. The bus interface unit of claim 24 in which another one of the control signals controls data flow from the receive buffer to the internal parallel bus.

26. The bus interface unit of claim 25 in which still another one of the control signals controls data flow from the internal parallel bus to the transmit buffer.

27. The bus interface unit of claim 26 in which still another one of the control signals controls data flow from the transmit shift register through the Manchester encoder/decoder to the biphase serial bus.

28. The bus interface unit of claim 27 in which still another one of the control signals controls a direction of data flow through the bidirectional buffer.

29. The bus interface unit of claim 28 in which still another one of the control signals controls data flow through the bidirectional buffer.

30. The bus interface unit of claim 29 which comprises at least one additional register responsive to the internal parallel bus.

31. The bus interface unit of claim 30 in which still another one of the control signals controls data flow from the internal parallel bus to the additional register.

32. The bus interface unit of claim 30 in which at least one of the logical signals is derived from the additional register.

33. A bus interface unit comprising:

decoding means having a biphase serial input port for receiving an incoming data stream in transition code format, means for converting the format of the incoming data stream from transition code to logic level, and an NRZ output through which the incoming data stream is output in logic level format;

means for deriving a word reception signal indicating when the incoming data stream is active;

means for deriving a word identification signal indicating when the incoming data stream contains a command sync;

encoding means having an NRZ input through which an outgoing data stream is input in logic level format, means for converting the format of the outgoing data stream from logic level to transition code, a biphase serial output port for transmitting the outgoing data stream in transition code format, a transmit enable input for controlling the outgoing data stream, and a sync select input for controlling a sync in the outgoing data stream;

means for deriving a word transmission signal indicating when the outgoing data stream is active;

means for deriving a bit count error signal indicating whether a defined segment of the incoming data stream includes a proper number of bits;

means for deriving a Manchester error signal indicating whether the defined segment of the incoming data stream includes any Manchester errors;

means for deriving a parity error signal indicating whether the defined segment of the incoming data stream has a proper parity;

a receive shift register having a serial receive input and a receive output, the serial receive input being connected to the NRZ output;

means for deriving a contiguous word signal indicating the presence of a contiguous word in the receive shift register;

a transmit shift register having a transmit input and a serial transmit output, the serial transmit output being connected to the NRZ input;

a parallel bus;

a parallel data port;

a bidirectional buffer connecting the parallel bus and the parallel data port, said bidirectional buffer having an enable buffer input for controlling data flow therethrough and a buffer direction input for controlling a direction of data flow between the parallel bus and the parallel data port;

a receive buffer having a receive buffer input responsive to the receive output, a receive buffer output connected to the parallel bus, a load receive buffer input responsive to the word reception signal for controlling data flow through the receive buffer input, and an enable receive buffer input for controlling data flow through the receive buffer output;

a transmit buffer having a transmit buffer input responsive to the parallel bus, a transmit buffer output connected to the transmit input, and a load transmit buffer input for controlling data flow through the transmit buffer input;

a status word register having a status address field responsive to an address field of the parallel bus, a status address enable input for controlling data flow from the status address field to the address field, and a status word field including a broadcast command bit, an error indicator bit, and a status error field having an unbuffered field responsive to the parallel bus and a buffered field responsive to a status buffer register, the status buffer register being responsive to the parallel bus, the unbuffered field including a dynamic bus control bit, the buffered field including a terminal flag bit, said status word register further including a status enable input for controlling data flow from the status word field to the parallel bus, a status load input for controlling data flow into the broadcast command and error indicator bits and from the status buffer register to the buffered field, and an address load input for controlling data flow from the parallel bus to the status address field, the unbuffered field and the status buffer register;

a command word register having a command word input responsive to the parallel bus, a command word output connected to the parallel bus, a load command word input for controlling data flow through the command word input, and an enable command word input for controlling data flow through the command word output;

a last command word register responsive to the command word register, and having a last command output connected to the parallel bus, an enable last command input for controlling data flow through the last command output, and a load last command input for controlling data flow from the command word register to the last command word register;

a mode code logic unit responsive to a mode code field and transmit/receive bit in the command word register and outputting a transmit last command mode signal, a dynamic bus control mode signal, a terminal flag inhibit mode signal, an override inhibit mode signal and a transmit status mode signal;

a mode code detector responsive to a subaddress field in the command word register and outputting a mode code detect signal;

an address compare logic unit responsive to an operating mode signal, the status address field, and corresponding address fields in the receive shift register, the receive buffer, and the command word register, said address compare logic unit outputting an address compare signal, a broadcast detect signal, and a command broadcast detect signal, the address compare signal indicating whether the address field of the receive buffer matches either a broadcast bit pattern or the status address field when the bus interface unit is operating in a remote terminal mode and whether the address field of the receive shift and command registers match when the bus interface unit is operating in a bus controller mode, the broadcast detect signal indicating whether the address field in the receive buffer matches the broadcast bit pattern when the bus interface unit is operating in the remote terminal mode and whether the address field in the command register matches the broadcast bit pattern when the bus interface unit is operating in the bus controller mode, and the command broadcast detect signal indicating whether the address field in the command register matches the broadcast bit pattern;

a counter response timer having a stop count input responsive to the word reception signal and a start count input and outputting a response time error signal;

an error register having seven error bits, an error enable input for controlling data flow from the error bits to an error field of the parallel bus, and a clear error input for clearing the error bits the first through fourth error bits respectively being responsive to the response time error signal, the bit count error signal, the Manchester error signal and the parity error signal, the error register outputting an error indicator signal indicating whether any of the error bits are set, the error indicator bit of the status word register being responsive to the error indicator signal;

a control register having first, second and third control bits responsive to the parallel bus and a load control code input for controlling data flow from the parallel bus to the control register;

a word counter responsive to the mode code field in the command word register and the mode code detect signal and having a load word count input for controlling data flow from the command word register to the word counter and a decrement input for decrementing a word count stored in the word counter, the word counter outputting a word count zero signal indicating when the word count is equal to zero;

a flag register having first through fifth flag bits, the first flag bit being responsive to the broadcast detect signal, the broadcast command bit of the status word register being responsive to the first flag bit, the fifth flag bit being responsive to the mode code detect signal, the flag register further having a clear command flag input for clearing the second flag bit, a clear toggle flag input for clearing the third flag bit, a load flag input for controlling the setting of the first and fifth flags, and a flag clear input for clearing the first, second, third and fifth flags;

a sequence logic unit having a logical AND array responsive to a command strobe signal, the operating mode signal, a bus grant acknowledge signal, a logical combination of the transmit last command mode and the mode code detect signals, a data transfer acknowledge signal, the word reception signal, the word identification signal, the address compare signal, the error indicator signal, the first, second and third flag bits, a logical combination of a designated bit in the mode code field and the transmit/receive bit in the command word register and the mode code detect, dynamic bus control mode, transmit status mode, operating mode, and command broadcast detect signals, the word count zero signal, the word transmission signal, the continguous word signal, and the first, second and third bits of the control register, the logical AND array outputting a plurality of logical product terms, the sequence logic unit further including a logical OR array responsive to the logical product terms and outputting a plurality of logical sum terms, the logical AND array further being responsive to a portion of the logical terms, the remaining sum terms defining an invalid message signal indicating the detection of errors in the incoming data stream, a write enable signal indicating a stable condition in the bidirectional buffer, a command strobe acknowledge signal indicating availability of the bus interface unit in response to the command strobe signal, a load timer signal, a data transfer request signal indicating availability of the parallel bus for data transfer from the parallel data port, a read/write signal indicating the direction of data flow between the parallel bus and the parallel data port, a command/data signal indicating a type of data flowing through the bidirectional buffer when the read/write signal indicates that data is flowing from the parallel bus to the parallel data port and otherwise indicating the completion of a data transfer from the parallel data port to the parallel bus, a message complete signal indicating when the outgoing data stream becomes inactive, a valid command signal indicating the reception of a valid command in the incoming data stream, a clear error/flag signal, an improper sync signal, an address mismatch signal, an improper word count signal, a load remote terminal address signal, an enable data signal, a load command signal, a load word counter signal, an enable command signal, an enable buffer signal, a strobe mode code signal, a status word load signal, a load transmit buffer signal, a shift word count signal, a transmit enable signal, a sync select signal, an enable status word signal, an enable last command signal, a load control word signal and a set toggle signal, the clear command flag input being responsive to a logical combination of the invalid message and message complete signals, the start count input of the counter response timer being responsive to the load timer signal, the buffer direction input being responsive to the read/write signal, the clear error and flag clear inputs being responsive to the clear error/flag signal, the fifth, sixth and seventh error bits respectively being responsive to the improper sync signal, the address mismatch signal, and the improper word count signal, the address load input of the status word register and the fourth flag bit of the flag register being responsive to the load terminal address signal, the enable receive buffer input being responsive to the enable data signal, the load command word and load last command inputs being responsive to the load command signal, the load word count and load flag inputs and the second flag bit being responsive to the load word counter signal, the enable command word input being responsive to the enable command signal, the enable buffer input being responsive to the enable buffer signal, the clear toggle flag and error enable inputs being responsive to the strobe mode code signal, the status load input being responsive to a logical combination of the transmit/receive bit in the command word register and the transmit last command mode, transmit status mode, mode code detect and status word load signals, the load transmit buffer input being responsive to the load transmit buffer signals, the load transmit buffer input being responsive to the load transmit buffer signal, the decrement input being responsive to the shift word count signal, the transmit enable and sync select inputs of the encoding means, respectively, being responsive to the transmit enable and sync select signals, the status enable input being responsive to the enable status word signal, the status address enable input being responsive to a logical combination of the enable status word and strobe mode code signals, the enable last command input being responsive to the enable last command signal, the load control code input being responsive to the load control word signal, and the third flag bit being responsive to a logical combination of the operating mode, load word counter and set toggle signals;

means for masking the dynamic bus control bit having a set dynamic bus mask input responsive to a logical combination of the fifth flag bit, the transmit/receive bit and the strobe mode code signal, and a clear dynamic bus mask input responsive to a logical combination of the transmit/receive bit, the mode code detect signal and the dynamic bus control mode signal;

means for masking the terminal flag bit having a set terminal flag mask input responsive to a logical combination of the terminal flag inhibit mode and strobe mode code signals and a clear terminal flag mask input responsive to a logical combination of the override inhibit mode and strobe mode code signals and the fifth flag bit;

means responsive to the transmit/receive and second flag bits, the mode code detect and message complete signals, and the transmit last command and transmit status mode signals for clearing all of the status error field except the dynamic bus control bit; and

means responsive to a power on reset signal for clearing the error and flag registers and the counter response timer.