Method for producing a MISFET

• US 4,453,305 A
• Filed: 07/12/1982
• Issued: 06/12/1984
• Est. Priority Date: 07/31/1981
• Status: Expired due to Fees

• Current Assignee: The secretary of state for defence in her Britannic Majesty's Government of the United Kingdom of Great Britain And Northern Ireland
• Original Assignee: The secretary of state for defence in her Britannic Majesty's Government of the United Kingdom of Great Britain And Northern Ireland
• Inventors: White, John C., Janes, Timothy W.
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US06/397,343
• Time in Patent Office: 701 Days
• Field of Search: 29/571, 29/580, 29/591, 156/626, 156/651, 148/1.5, 148/187
• US Class Current: 438/282
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method for producing a MISFET having a gate electrode formed at the base of a grooved recess. The grooved recess is formed with steep side-walls (e.g., be reactive ion etching, ion beam milling or by using an orientation dependent etchant) and gate and source and drain contacts are formed by the simultaneous deposition of conductive material (e.g., metal evaporated from a point source.) Steepness of the side-walls of the recess ensures separation of the conductive material, isolating the gate electrode from the remaining conductive material providing the source and drain contacts.

A silicon MISFET may be produced, using a diazine catalyzed ethylenediamine-pyrocatechol-water solution etchant, and exposing the (110) crystal plane face of the silicon to the etchant to form the recess.

Claims

1. A method for producing a MISFET (metal-insulator-semiconductor field-effect transistor), the method comprising the following steps:

(a) providing a substrate of single crystal semiconductor material;

forming an excess doped region of semiconductor material of opposite conductivity type for

(b) providing the source and drain regions of the MISFET;

(c) forming, between and immediately adjacent the source and drain regions, a steep-walled groove extending depthwise at least to the interface between the excess doped material and the underlying substrate material;

(d) forming an insulating layer over the surface of the groove and over the excess doped material, windows being provided in the layer to expose the source and drain regions of the excess doped material;

(e) depositing conductive material so to cover simultaneously the exposed source and drain regions and the base of the groove, to exclusion of the steep side-walls of the groove; and

(f) annealing the whole to consolidate the contact junctions between the conductive material and the excess doped material.

2. A method as claimed in claim 1 wherein the steep-walled groove is formed by etching, using an orientation dependant etchant to define the steep side walls of the groove.

3. A method as claimed in claim 2 wherein the substrate and the doped region are silicon semiconductor material, and the etchant is a diazine catalyzed ethylenediamine-pyrocatechol-water solution;

the steep-walled groove being formed exposing (110) crystal plane face of the doped silicon material to the etchant through a mask window the edges of which are aligned with {111} crystal planes.

4. A method as claimed in claim 3 wherein an electrical bias is applied across the doped silicon interface to stop etching action when the groove extends depthwise to the interface.

5. A method as claimed in claim 4 wherein the bias is removed once the etching action has stopped, and etching recontinued for a controlled period of time.

6. A method as claimed in claim 4 wherein once the etching action has stopped the pyrocatechol etchant is replaced by a slow-action etchant and etching recontinued.

7. A method as claimed in claim 1 wherein the conductive material is a metal, and is deposited by evaporation from a point source.